Hierarchical Routing Matrices for High-Throughput Pattern Recognition
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Solution Overview
Problem
Conventional pattern-recognition processors face challenges in meeting performance requirements due to non-configurable physical connections between finite state machines, which lead to bottlenecks in processing large volumes of data with increasing numbers of patterns, slowing down data receipt.
Innovation Solution
Implement a multi-level hierarchical routing matrix architecture in pattern-recognition processors, utilizing programmable connections and parallel finite state machines to evaluate multiple search criteria simultaneously, enabling high-bandwidth data processing without performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional physical wire connections are used between finite state machines, then device complexity is reduced, but processing speed and configurability deteriorate
Solution Approach 1:
A routing matrix is introduced as an intermediary component between finite state machines and memory elements. This routing matrix dynamically directs data flow through programmable connections, enabling reconfigurable data paths without requiring dedicated physical wires between each FSM and memory element, thus improving processing speed while managing complexity.
Solution Approach 2:
The connection architecture transitions from static physical wire connections to dynamic programmable routing. The routing matrix can be reconfigured at runtime to establish different data paths between FSMs and memory elements, allowing the system to adapt to different processing requirements and improve overall processing speed through optimal routing configurations.
2Adaptability or versatility
If the number of patterns increases to detect more spam and malware variants, then detection capability improves, but processing time increases
Solution Approach 1:
The system segments pattern matching operations across multiple finite state machines that operate in parallel. Each FSM can handle specific patterns or pattern groups, allowing simultaneous evaluation of multiple search criteria. This parallel processing approach enables detection of increasing numbers of patterns without proportionally increasing processing delay.
Solution Approach 2:
Pattern matching criteria are pre-compiled into finite state machine configurations before data processing begins. This preliminary preparation allows the system to rapidly evaluate pre-defined patterns against incoming data streams without requiring complex runtime compilation or interpretation, reducing processing delay while maintaining high pattern detection capability.
3Productivity
If sequential pattern searching is used, then device complexity is minimized, but productivity deteriorates
Solution Approach 1:
Multiple finite state machines are merged into a single integrated processor architecture with shared memory elements and routing resources. This consolidation enables parallel pattern evaluation while avoiding the complexity of completely separate processing units, thereby improving data processing throughput through efficient resource utilization and coordinated operation.
Solution Approach 2:
The finite state machines and routing matrix are designed as universal, reconfigurable components that can handle multiple pattern types and data formats. This multi-functionality allows a single processor architecture to efficiently process diverse patterns (spam, malware, etc.) in parallel, significantly improving productivity without requiring specialized hardware for each pattern type.
Data Source
AI summary
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.