Hierarchical Routing Matrices for Parallel Pattern Search
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Solution Overview
Problem
Conventional pattern-recognition processors face performance bottlenecks due to the increasing number of patterns to be identified in data streams, as they rely on physical wires and finite state machines that are not configurable or capable of meeting the required speed and configurability for efficient pattern search.
Innovation Solution
A multi-level hierarchical routing matrix architecture is introduced, allowing for parallel processing of multiple search criteria and dynamic reconfiguration of connections between feature cells, enabling efficient evaluation of large numbers of search terms without a significant increase in search-cycle duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional physical wires and finite state machines are used for pattern recognition, then the processor can be manufactured with standard silicon technology, but the processing speed decreases and configurability is limited as the number of patterns increases
Solution Approach 1:
The patent implements dynamic reconfiguration of the routing matrix connections, allowing the processor to adapt its internal connectivity pattern based on the specific search criteria being evaluated. This enables the same hardware structure to be dynamically reconfigured for different pattern recognition tasks, resolving the contradiction between fixed manufacturing and flexible adaptability.
Solution Approach 2:
The routing matrix architecture serves multiple functions: it acts as both a connection network and a programmable logic element. The same physical structure can be configured to implement different state machine behaviors and pattern matching logic, providing universal functionality across various pattern recognition applications without requiring separate dedicated hardware for each function.
2Productivity
If multiple search criteria are processed sequentially using conventional architecture, then the device complexity remains manageable, but the processing time increases significantly
Solution Approach 1:
The patent segments the pattern recognition process into parallel evaluation units that can simultaneously process different search criteria. The routing matrix is divided into multiple configurable paths, each capable of evaluating a different pattern independently, allowing sequential search criteria to be processed in parallel without increasing overall device complexity.
Solution Approach 2:
The architecture implements a nested structure where multiple levels of pattern matching are organized hierarchically. Simpler pattern matching operations are nested within more complex evaluation stages, allowing the system to process multiple search criteria through layered evaluation rather than requiring a completely flat, complex parallel structure.
3Adaptability or versatility
If the number of patterns to be searched increases, then the recognition capability improves, but the delay before the system is ready to search the next portion of data stream increases
Solution Approach 1:
The routing matrix architecture enables continuous evaluation of multiple patterns simultaneously through parallel signal paths. As data flows through the processor, multiple pattern matching operations occur concurrently without requiring sequential completion, eliminating the delay that would normally occur while waiting for one pattern search to finish before starting the next.
Solution Approach 2:
The system performs preliminary configuration of the routing matrix connections based on the search criteria being evaluated. By pre-configuring the appropriate connection patterns before data arrival, the system prepares multiple evaluation paths in advance, allowing immediate parallel processing when data is received without requiring reconfiguration delays.
Data Source
AI summary
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.