Probabilistic Shaping Decoding Circuit Using Hierarchical LUTs
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Solution Overview
Problem
Conventional probabilistic shaping decoding circuits experience performance degradation and increased circuit scale when the number of input/output bits of lookup tables (LUTs) is small, deviating from the Shannon limit or requiring excessive SNR for transmission capacity.
Innovation Solution
A probabilistic shaping decoding circuit with hierarchized lookup tables and additional distribution and address replacing circuits, reducing circuit scale while maintaining performance by converting bit strings through a tree-shaped structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of input/output bits of each LUT is increased to prevent performance degradation, then the transmission capacity approaches the Shannon limit, but the circuit scale increases
Solution Approach 1:
The patent divides the LUT into multiple sub-LUTs, each handling a portion of the address bits. Instead of using a single large LUT that would require excessive circuit scale, the address is segmented and distributed to multiple smaller sub-LUTs that work together to produce the final output, thereby reducing the circuit scale of individual components while maintaining overall transmission capacity
Solution Approach 2:
The patent implements a hierarchical structure where sub-LUTs are nested within the overall LUT architecture. The output of sub-LUTs is combined through addition operations to form the final LUT output, creating a nested structure that efficiently utilizes circuit resources while achieving the required transmission capacity without excessive scale
2Device complexity
If the number of input/output bits of each LUT is decreased to reduce circuit scale, then the circuit scale is reduced, but performance degradation occurs in probabilistic distribution shaping
Solution Approach 1:
The patent combines the outputs of multiple sub-LUTs through addition operations to produce the final LUT output. By merging the results from multiple smaller sub-LUTs, the system achieves the equivalent functionality of a large LUT while using smaller, more efficient components that reduce overall circuit scale
3Ease of operation
If a single LUT is used, then the lookup operation is simple, but the circuit scale of the LUT exponentially increases as the number of input/output bits increases
Solution Approach 1:
The patent segments the address bits and distributes them to multiple sub-LUTs, each performing simple lookup operations on their respective portions. This segmentation maintains the simplicity of individual lookup operations while avoiding the exponential circuit scale growth that would occur with a single large LUT
Data Source
AI summary
The circuit includes (2m−1)-th and 2m-th lookup tables of a layer x to restore (2m−1)-th and 2m-th reception address bit strings of the layer x and (2m−1)-th and 2m-th reception information bit strings of the layer x; an m-th address conversion lookup table of the layer x to convert the (2m−1)-th reception address bit string of the layer x into that of post-conversion; an m-th adder of the layer x to add the (2m−1)-th post-conversion reception address bit string of the layer x and the 2m-th reception address bit string of the layer x and output an addition result as an m-th reception shaping bit string of a layer x+1; and an m-th lookup table of the layer x+1 to restore an m-th reception address bit string of the layer x+1 and an m-th reception information bit string of the layer x.