Hierarchical SRAM Bitline Layout for Lower RC Loss and Write Margin
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Solution Overview
Problem
Conventional SRAM designs face challenges in achieving improved Energy-Delay-Area-Product (EDAP) due to increased sub-array sizes leading to longer word lines and bit lines, which result in resistive and capacitive losses and degraded write margins.
Innovation Solution
The SRAM device employs a hierarchical word line and bit line structure with local selection mechanisms and additional logic transistors stacked over frontend transistors, allowing for larger sub-arrays while maintaining write margins and reducing RC losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sub-array size is increased to reduce inter-sub-array interconnect routing overhead, then EDAP is improved, but word line and bit line length increase leading to resistive and capacitive losses and degraded write margins
Solution Approach 1:
The patent divides the sub-array into multiple local blocks, each with its own local word lines and local bit lines. This segmentation reduces the length of individual word lines and bit lines within each local block, thereby reducing resistive and capacitive losses while maintaining the overall larger sub-array size for reduced interconnect overhead.
Solution Approach 2:
The patent introduces a hierarchical structure with local and global word lines/bit lines operating at different levels. The local word lines/bit lines serve small local blocks, while global word lines/bit lines coordinate across multiple local blocks. This multi-level hierarchical approach enables the system to achieve benefits of both small local structures (low RC losses) and large global structures (reduced interconnect overhead).
2Productivity
If sub-array size is increased to reduce inter-sub-array interconnect routing overhead, then EDAP is improved, but interconnect RC losses increase
Solution Approach 1:
By segmenting the sub-array into local blocks with dedicated local word lines and bit lines, the patent minimizes the RC losses within each local block. The segmentation ensures that signal paths remain short locally, reducing energy loss from resistance and capacitance effects.
Solution Approach 2:
The patent introduces local word lines and local bit lines as intermediary structures between the global word lines/bit lines and the actual bit cells. These intermediaries enable selective activation of only the necessary local blocks, reducing the overall capacitive loading and energy dissipation in the interconnect network.
3Area of stationary object
If conventional SRAM design is used with larger sub-arrays, then area efficiency is improved, but write margin is degraded due to longer word lines and bit lines
Solution Approach 1:
The patent segments the large sub-array into multiple smaller local blocks, each with its own local word lines and bit lines. This segmentation maintains area efficiency by packing bit cells densely within each local block while ensuring that the word line and bit line lengths within each block remain short, thereby preserving write margin despite the overall large sub-array size.
Solution Approach 2:
The patent transitions from a flat, single-level word line/bit line structure to a hierarchical multi-level structure. This dimensional change allows the system to achieve both large area efficiency and small local signal paths by operating at multiple hierarchical levels simultaneously.
Data Source
AI summary
In an aspect there is provided an SRAM device comprising: a plurality of hierarchical word line structures (HWLs), each comprising a global word line (GWL), and a plurality of local word lines (LWLs); a plurality of hierarchical bit line structures (HBLs), each comprising a global bit line (GBL), a plurality of local bit lines (LBLs), a global bit line bar (GBLB), and a plurality of local bit line bars (LBLBs); a plurality of local block column select lines (LBCSs); a plurality of local block row select lines (LBRSs); and an SRAM bit cell array comprising a plurality of bit cells arranged in a plurality of array rows and array columns, each array row associated with a respective HWL and each array column associated with a respective HB.