Hierarchical SRAM Array Layout for Lower RC Loss and Write Margin
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Solution Overview
Problem
Conventional SRAM designs face challenges in achieving improved Energy-Delay-Area-Product (EDAP) due to increased sub-array sizes leading to longer word and bit lines, which result in resistive and capacitive losses and degraded write margins, while attempts to mitigate these issues through larger sub-arrays lead to write failure problems.
Innovation Solution
The SRAM device employs a hierarchical word and bit line structure with local selection mechanisms and additional logic transistors stacked over frontend transistors, allowing for larger sub-arrays with reduced RC losses and maintained write margins by using backend and frontend transistor stacking techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of SRAM sub-arrays is increased to reduce inter-sub-array interconnect routing overhead, then the Energy-Delay-Area-Product (EDAP) is improved, but the word lines and bit lines become longer which increases resistive and capacitive losses and degrades write margins
Solution Approach 1:
The SRAM array is divided into multiple sub-arrays, each with its own hierarchical word line and bit line structures. This segmentation allows each sub-array to be smaller, reducing the length of interconnect lines within each sub-array and thereby reducing resistive and capacitive losses, while still achieving the desired overall array size for improved EDAP.
Solution Approach 2:
The patent introduces a hierarchical structure with global and local word lines/bit lines, adding a dimensional layer to the traditional flat interconnect architecture. This hierarchical dimension allows for better routing optimization and reduced interconnect length within each sub-array, addressing the write margin issue while maintaining improved EDAP.
2Productivity
If conventional SRAM designs use larger sub-arrays to improve EDAP, then interconnect routing overhead is reduced, but resistive and capacitive losses increase leading to write failure problems
Solution Approach 1:
By segmenting the SRAM array into multiple sub-arrays with hierarchical interconnect structures, the patent reduces the length of word lines and bit lines within each sub-array. This segmentation directly reduces resistive and capacitive losses, allowing larger overall array sizes to achieve improved EDAP without suffering from excessive energy losses.
Solution Approach 2:
The patent changes the interconnect architecture parameters by introducing hierarchical word line and bit line structures with both global and local components. This parameter change optimizes the interconnect length and routing efficiency, reducing resistive and capacitive losses while enabling larger sub-arrays for improved EDAP.
Data Source
Figure 1a~1b
Figure 2a
Figure 2b~2c
AI summary
In an aspect there is provided an SRAM device comprising: a plurality of hierarchical word line structures, HWLs, each comprising a global word line, GWL, and a plurality of local word lines, LWLs; a plurality of hierarchical bit line structures, HBLs, each comprising a global bit line, GBL, a plurality of local bit lines, LBLs, a global bit line bar, GBLB, and a plurality of local bit line bars, LBLBs; a plurality of local block column select lines, LBCSs; a plurality of local block row select lines, LBRSs; and an SRAM bit cell array comprising a plurality of bit cells arranged in a plurality of array rows and array columns, each array row associated with a respective HWL and each array column associated with a respective HBL, wherein the SRAM bit cell array is partitioned into a plurality of local blocks, each local block associated with a respective LBCS and LBRS, and each comprising a respective subset of bit cells arranged in a plurality of local rows and local columns, each local row comprised in one of the array rows and connected to a respective LWL of the HWL associated with the array row, each local column comprised in one of the array columns and connected to a respective LBL and LBLB of the HBL associated with the array column; for each local column of each local block, a first switch and a second switch, the first switch configured to selectively connect the LBL connected to the local column to its associated GBL, and the second switch configured to selectively connect the LBLB connected to the local column to its associated GBLB; and for each local block, a respective logic circuit configured to individually assert a LWL connected to a local row of the local block in response to the LBCS and LBRS associated with the local block, and the GWL associated with the LWL being simultaneously asserted; wherein each bit cell comprises cross-coupled inverters and pass gates, the inverters and pass gates comprising a first set of transistors arranged in a front-end-of-line, FEOL, structure of a die of the SRAM device; and wherein the first and second switches and the logic circuits comprise a second set of transistors arranged in one or more device tiers over the FEOL structure.