Hierarchical Finite State Machines for Reduced State Vector Transfer
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Solution Overview
Problem
Hierarchical parallel machines face challenges in reducing data processing time due to the large amount of state information passed between finite state machine engines, which can lead to delays in real-time operations, especially as the size of the state machines increases.
Innovation Solution
Implementing a hierarchical structure with cascaded finite state machine engines where each level processes and provides output based on lower-level analysis, allowing feedback for learning and optimizing state machine implementations to reduce the size of state vectors passed between engines, and using methods like aggregation and compression to minimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of state machines increases to improve pattern recognition capability, then the recognition accuracy is improved, but the data processing time increases due to larger state vectors being passed between engines
Solution Approach 1:
The patent divides the large state machine into multiple hierarchical levels, where each level processes a portion of the state information. The state vector is segmented and processed in stages through different engine levels, reducing the amount of data that needs to be transferred at any single interface while maintaining overall recognition accuracy.
Solution Approach 2:
The patent introduces a hierarchical dimension to the state machine architecture, organizing engines into multiple levels rather than a single flat structure. This dimensional change allows state information to be processed through vertical hierarchy, reducing horizontal data transfer requirements and enabling parallel processing at different levels.
2Reliability
If the size of state vectors passed between engines increases to maintain complete state information, then the reliability of state tracking is improved, but the data transfer volume increases causing delays
Solution Approach 1:
The patent extracts only the essential state information needed for each processing level, removing redundant data from the state vectors passed between engine levels. Each level receives and processes only the specific state elements relevant to its function, maintaining reliability while minimizing data transfer volume.
Solution Approach 2:
The patent implements partial state information transfer between engine levels, where each level receives sufficient state data to perform its specific processing function without obtaining the complete state vector. This partial action approach maintains adequate reliability for each level's operations while significantly reducing data transfer requirements.
3Speed
If a hierarchical structure is implemented to reduce data transfer, then the data processing speed is improved, but the device complexity increases due to multiple engine levels
Solution Approach 1:
The patent designs the hierarchical engine levels with universal, standardized interfaces and processing capabilities. Each engine level can handle multiple types of state information and communicates through standardized protocols, reducing the complexity overhead of the hierarchical structure by enabling multi-functional processing at each level.
Solution Approach 2:
The patent implements a nested hierarchical structure where engine levels are organized in a compact, integrated manner. Lower-level engines are nested within or closely coupled to higher-level engines, allowing state information to flow through predefined hierarchical paths and reducing the complexity of inter-engine communication by establishing clear nesting relationships.
Data Source
AI summary
Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.