Hierarchical Static Timing Analysis Clock Re-convergence Pessimism Removal

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Solution Overview

Problem

Hierarchical static timing analysis (HSTA) faces challenges in accurately performing clock re-convergence pessimism removal (CRPR) due to dependence on both clock timing and topology, as conventional block-level analysis cannot provide accurate CRP values when common points are located in other blocks or hierarchies, leading to overly pessimistic or optimistic timing calculations.

Innovation Solution

The method involves dividing the clock network into blocks with a top level containing additional clock components, performing block-level and top-level analysis iteratively, and requesting and sending CRPR data between levels to correct overly pessimistic or optimistic calculations, ensuring accurate timing information across multiple hierarchies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional block-level analysis is used in HSTA, then analysis complexity is reduced and processing is more manageable, but timing accuracy deteriorates due to inability to see complete clock network topology

Engineering Contradiction:
Improveanalysis complexityVSAvoidtiming accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The clock network is segmented into block-level and top-level components. Block-level analysis handles individual blocks with their local clock topology, while top-level analysis handles the global clock network. This segmentation allows manageable analysis complexity at each level while maintaining timing accuracy through coordinated multi-level processing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The analysis is extended from a single block level to multiple hierarchical dimensions. By adding the top-level analysis dimension that encompasses all blocks, the system gains visibility of the complete clock network topology while maintaining the organizational benefits of block-level segmentation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If complete clock network topology is considered for accurate CRPR, then timing accuracy improves, but analysis complexity and memory usage increase significantly

Engineering Contradiction:
ImproveCRPR accuracyVSAvoidanalysis complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The clock network analysis is segmented into block-level and top-level components. Each level performs CRPR analysis on its visible portion of the clock network, avoiding the need to load and analyze the complete clock network at once. This reduces memory usage and analysis complexity while maintaining accuracy through coordinated processing across levels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each analysis level performs partial CRPR analysis on the portion of the clock network visible to it. Block-level analysis performs CRPR on local clock paths, and top-level analysis performs CRPR on global clock paths. The combination of these partial analyses achieves complete CRPR accuracy without requiring complete network visibility at each step.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If iterative multi-level analysis is performed to exchange CRPR data between blocks and top level, then timing accuracy improves, but processing time increases

Engineering Contradiction:
Improvetiming accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

CRPR data is calculated and exchanged between block-level and top-level analyses in an iterative manner. The preliminary CRPR calculations at each level provide initial accuracy, and subsequent iterations refine the results. This preliminary action at each level reduces the need for extensive repeated analysis, balancing accuracy with processing time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8813011B2Clock-reconvergence pessimism removal in hierarchical static timing analysis
Publication Date: 2014.08.19 SYNOPSYS INC
  • US8813011B2 patent drawing
  • US8813011B2 patent drawing
  • US8813011B2 patent drawing

AI summary

A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.