Hierarchical Store Queue Circuit with Tiered Forwarding
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Solution Overview
Problem
Increasing the size of a store queue in integrated circuit designs, such as system-on-chip (SoC), leads to undesirable impacts on die area, clock signal timing, and power consumption due to complex circuitry required for store-to-load forwarding.
Innovation Solution
Implementing a hierarchal store queue structure with a fast primary queue and a simpler secondary queue, where older store requests are maintained in the primary queue for rapid store-to-load forwarding, and younger requests are buffered in the secondary queue, using simpler circuitry to reduce the negative impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the store queue size is increased to improve buffering capacity, then the queue can hold more store requests, but die area, power consumption, and timing constraints deteriorate due to complex circuitry required for store-to-load forwarding
Solution Approach 1:
The store queue is divided into two distinct segments: a primary store queue with full store-to-load forwarding capability and a secondary store queue with simplified circuitry. This segmentation allows the system to increase overall buffering capacity while limiting the complexity growth to only the necessary portion of the queue.
Solution Approach 2:
Different portions of the store queue are assigned different levels of functionality and complexity. The primary queue maintains full forwarding capability for critical operations, while the secondary queue uses simpler circuitry for less time-sensitive buffering, optimizing the balance between capacity and complexity.
2Quantity of substance
If the store queue size is increased to buffer more store requests, then more requests can be held awaiting cache update, but power consumption increases due to the larger and more complex circuitry
Solution Approach 1:
The store queue is segmented into primary and secondary portions, allowing the system to increase total buffering capacity while keeping the power-consuming complex forwarding circuitry limited to only the primary queue where it is most needed.
Solution Approach 2:
Power consumption is optimized by applying full forwarding capability only locally to the primary queue where time-sensitive operations occur, while the secondary queue uses lower-power simplified circuitry for less critical buffering operations.
3Quantity of substance
If the store queue size is increased to improve performance, then more store requests can be buffered, but timing constraints worsen due to the increased complexity affecting clock signal timing
Solution Approach 1:
The store queue is segmented into primary and secondary portions, allowing the system to increase total buffering capacity while limiting the timing-critical complex forwarding circuitry to only the primary queue, thereby maintaining acceptable timing constraints.
4Speed
If the primary queue is optimized for rapid store-to-load forwarding, then critical load requests can be serviced quickly, but die area increases due to the complex forwarding circuitry
Solution Approach 1:
The store queue is segmented into a primary portion with full forwarding capability optimized for speed, and a secondary portion with simplified circuitry. This allows rapid servicing of critical load requests from the primary queue while containing the die area impact of complex circuitry to only where it provides the most value.
Solution Approach 2:
The primary queue is locally optimized with complex forwarding circuitry for rapid store-to-load forwarding of critical requests, while the secondary queue uses simpler circuitry, thereby achieving high speed where needed while minimizing overall die area consumption.
Data Source
AI summary
An apparatus includes a cache memory circuit, and a hierarchal store queue circuit that further includes a primary queue and a secondary queue. The hierarchal store queue circuit may be configured to write incoming store requests to the primary queue in response to the primary queue currently having capacity, and to write incoming store requests to the secondary queue in response to the primary queue currently not having capacity. The hierarchal store queue circuit may be further configured to commit store requests to the cache memory circuit from the primary queue but not from the secondary queue. In response to a determination that the primary queue currently has capacity, the hierarchal store queue circuit may perform a transfer of at least one store request from the secondary queue to the primary queue.