Hierarchical TCD Cell Placement Using Overlap Detection

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Solution Overview

Problem

The placement of test-key critical dimension (TCD) cells in semiconductor integrated circuits often results in invalid placements due to misalignment between hierarchical layers, leading to extended design periods and validation errors.

Innovation Solution

A design apparatus and method that identifies overlapping areas in the highest hierarchical layer to set temporary placement locations for dummy TCD cells, optimizing placement to minimize invalid placements and reduce the need for repeated assembly and validation in lower hierarchical layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TCD cells are placed in the lowest hierarchical layer following DRC placement rules, then manufacturing variation monitoring is enabled, but invalid placements occur due to overlapping and misalignment issues in hierarchical assembly

Engineering Contradiction:
Improveplacement validityVSAvoidhierarchical assembly complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by detecting overlapping areas and setting temporary placement locations for TCD cells in the lowest hierarchical layer before final assembly. This advance preparation prevents invalid placements during hierarchical assembly, reducing the need for repeated validation and improving placement validity while managing assembly complexity.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If validation is performed in the highest hierarchical layer after assembly, then placement correctness is verified, but design period extends due to repeated assembly and validation cycles

Engineering Contradiction:
Improveplacement validation accuracyVSAvoiddesign period
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary detection of overlapping areas and temporary placement of TCD cells in the lowest hierarchical layer before hierarchical assembly. This preliminary action ensures placement correctness is verified in advance, reducing the need for repeated validation cycles in the highest hierarchical layer and shortening the overall design period while maintaining validation accuracy.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If TCD cells are placed in site areas considering power supply in lowest hierarchical layer, then power distribution is optimized, but overlapping issues arise during hierarchical assembly

Engineering Contradiction:
Improvepower supply integrationVSAvoidplacement alignment
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by detecting overlapping areas and setting temporary placement locations for TCD cells before final hierarchical assembly. This allows power supply optimization in site areas of the lowest hierarchical layer while preventing placement alignment issues during assembly, as the temporary placements are adjusted to avoid overlaps before commitment to final positions.

Inventive Principle:
Principle #10Preliminary action

4Adaptability or versatility

If hierarchical design is conducted with TCD cells in lowest layer, then design reusability is improved, but invalid placements increase due to segment division misalignment

Engineering Contradiction:
Improvedesign reusabilityVSAvoidplacement validity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent performs preliminary detection of overlapping areas and temporary placement of TCD cells in the lowest hierarchical layer before hierarchical assembly. This preliminary action maintains design reusability through hierarchical design while preventing invalid placements caused by segment division misalignment, as overlapping areas are identified and adjusted before final assembly commitment.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12632633B2Method and design apparatus
Publication Date: 2026.05.19 FUJITSU LTD
  • US12632633B2 patent drawing
  • US12632633B2 patent drawing
  • US12632633B2 patent drawing

AI summary

A processing unit reads out design information about a highest hierarchical layer from a storage unit, divides the highest hierarchical layer into a plurality of segments (segments, etc.) based on the design information about the highest hierarchical layer, detects overlapping areas (optimum placement areas) in which segments at a corresponding location among a plurality of instances in a lowest hierarchical layer included in the highest hierarchical layer overlap with each other at least partly when the plurality of instances are overlapped with each other, sets, in each of the overlapping areas in the plurality of instances, a temporary placement location in which a test cell used for testing of manufacturing variation in critical dimension is temporarily placed, and outputs information indicating the overlapping areas and the temporary placement locations.