Hierarchical Thermometer Decoder Circuit With Shorter Critical Paths
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Solution Overview
Problem
Existing decoder circuits for converting n-bit binary inputs into 2n-bit thermometer outputs become excessively complex and large as the number of bits increases, leading to increased circuit size and propagation delays, making them inefficient for handling varying bit lengths effectively.
Innovation Solution
An n-bit decoder circuit is designed using 2n base circuits and an (n−1)-bit decoder circuit, where selection signals determine the output, allowing for a simpler and more flexible configuration that maintains a smaller circuit size proportional to 2×2n−3, and reduces critical path length to n, enabling easy design adjustments with changing bit lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional decoder circuit methods (Method 1 or Method 2) are used to convert n-bit binary inputs into 2n-bit thermometer outputs, then the decoder circuit can be realized, but the circuit size increases proportionally to n×2n and the configuration becomes extremely complicated as the number of bits increases
Solution Approach 1:
The decoder circuit is segmented into multiple stages, where each stage processes a portion of the binary input bits. Instead of implementing a single complex n-bit decoder, the circuit divides the decoding task into several simpler sub-decoders that work in sequence, reducing the complexity of individual stages while maintaining the overall functionality of converting n-bit binary to 2n-bit thermometer code.
Solution Approach 2:
The patent employs a nested structure where smaller decoder units are embedded within larger decoder stages. Each stage contains decoder circuits that are themselves composed of smaller decoder units, creating a hierarchical nesting pattern. This nesting allows the complex n-bit decoding function to be built from simpler, reusable building blocks, reducing overall circuit complexity.
2Ease of manufacture
If conventional decoder circuit methods are used, then the decoder circuit can be realized, but the circuit size becomes excessively large proportional to n×2n
Solution Approach 1:
The decoder circuit is divided into multiple functional segments that process different aspects of the decoding operation. By segmenting the circuit into specialized units (such as partial decoders, selection logic, and output generation stages), the patent reduces the area required for each segment while maintaining the complete decoding functionality, thus reducing the total circuit size from the conventional n×2n proportion.
Solution Approach 2:
The patent designs universal decoder units that can perform multiple functions within a single circuit block. These multi-functional units can handle different bit positions and decoding operations, reducing the need for separate dedicated circuits for each function, thereby minimizing the overall circuit area while maintaining full decoding capability.
3Ease of manufacture
If conventional decoder circuit methods are used, then the decoder circuit can be realized, but the critical path length increases leading to increased propagation delays
Solution Approach 1:
The decoding process is segmented into multiple parallel stages, where each stage completes a portion of the decoding task. By breaking the critical path into shorter segments that can operate in parallel, the patent reduces the overall propagation delay compared to a single-stage conventional decoder, as the longest path through the circuit is now limited to the duration of the slowest stage rather than the entire decoding process.
Solution Approach 2:
The patent implements preliminary processing stages that prepare intermediate results before the final decoding operation. By performing preliminary actions such as partial decoding, bit selection, and intermediate calculations in advance, the circuit reduces the workload and propagation delay of the critical path stages, allowing the main decoding function to be completed more quickly.
Data Source
AI summary
The n-bit decoder circuit includes 2n base circuits each outputting, as the output signal OA, ‘0’, ‘1’ or the input signal IA depending on setting of selection signals S<1:0>; and the (n−1)-bit decoder circuit. The (n−1)-bit decoder circuit includes 2(n-1) base circuits and an (n−2)-bit decoder circuit in cases of n≥3, and includes the 1-bit decoder circuit in cases of n=2. The 1-bit decoder circuit outputs ‘00’ in cases of the binary input BIN<0>=‘0’ and outputs ‘01’ in cases of the binary input BIN<0>=‘1’ as thermometer outputs THM(1)<1:0>.