Hierarchical Throttle Controller for Multi-Core Voltage Noise
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Solution Overview
Problem
In multi-core processors, unsynchronized throttling actions can lead to power system noise and performance issues when transitioning from a throttled to an unthrottled state, due to unsynchronized power management and voltage fluctuations.
Innovation Solution
A modular, hierarchical system of throttle controllers within processor cores dynamically adjusts execution suspension, with a chip controller synchronizing throttling actions across cores to manage voltage noise, power, and thermal aspects, using staggered throttle terminations to avoid large current changes and induce synchronized transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If frequency and voltage scaling are used to adjust power consumption, then power consumption is reduced, but power system noise and other effects increase
Solution Approach 1:
The throttle control system is divided into multiple hierarchical levels (chip-level, core-level, and functional unit-level) that independently manage throttling decisions. This segmentation allows power consumption to be reduced through coordinated throttling while distributing the control logic to minimize noise generation from centralized voltage/frequency scaling operations.
Solution Approach 2:
The system dynamically adjusts execution suspension at multiple granularities based on real-time power, thermal, and performance conditions. Rather than relying solely on frequency/voltage scaling, the system dynamically throttles execution at different hierarchical levels to reduce power consumption while maintaining stability and minimizing noise through adaptive control.
2Use of energy by moving object
If unsynchronized throttling actions are implemented across processor cores, then power consumption is reduced, but power system noise and performance issues increase due to voltage fluctuations
Solution Approach 1:
The chip-level throttle controller merges and coordinates throttling actions across multiple processor cores, ensuring synchronized execution suspension. This coordination prevents unsynchronized power draw changes that cause voltage fluctuations, while still achieving overall power consumption reduction through unified control of multiple cores.
Solution Approach 2:
The system implements feedback mechanisms where the chip-level controller monitors power conditions, thermal events, and performance metrics across all cores, then adjusts throttling actions accordingly. This feedback loop ensures that throttling is synchronized across cores to prevent voltage fluctuations while maintaining effective power management.
3Stability of the object's composition
If a centralized throttle control system is used, then coordination between cores is improved, but device complexity increases
Solution Approach 1:
The throttle control system is segmented into hierarchical levels with distributed intelligence. Chip-level controllers handle inter-core coordination, while core-level and functional unit-level controllers manage local throttling decisions. This segmentation reduces overall system complexity by distributing control logic rather than requiring a single complex centralized controller.
Solution Approach 2:
The system implements a nested hierarchical structure where chip-level controllers contain multiple core-level controllers, which in turn contain functional unit-level controllers. Each level operates semi-independently with well-defined interfaces, allowing coordination between cores while keeping individual controller units relatively simple and manageable.
4Manufacturing precision
If fine-grained execution suspension is implemented, then power management precision is improved, but device complexity increases
Solution Approach 1:
Fine-grained execution suspension is achieved by segmenting the throttle control into functional unit-level controllers within each core. Each functional unit can be independently throttled based on local power and performance conditions, providing precise power management at the finest granularity without requiring a single complex controller to manage all details.
Solution Approach 2:
The system adds hierarchical dimensionality to throttle control, operating at chip-level, core-level, and functional unit-level simultaneously. This multi-dimensional approach enables fine-grained power management precision by controlling execution suspension at the functional unit level, while the hierarchical structure keeps individual controller complexities manageable through clear separation of concerns.
Data Source
AI summary
An aspect includes a plurality of throttle controllers having a modular hierarchy comprising a plurality of levels within each of a plurality of processor cores that control a plurality of throttling actions. The throttling actions include dynamic adjustment of execution suspension within the processor cores. A plurality of input throttle events at each of the processor cores is resolved based on the modular hierarchy. A chip controller coupled to the processor cores can synchronize the throttling actions between the processor cores.