Hierarchical Tiling Engine for Graphics Memory Bandwidth
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Solution Overview
Problem
Tile-based rendering (TBR) graphics processing systems face challenges in managing memory bandwidth due to the need to store transformed geometry data for an entire frame, which requires significant data transfer between the geometry processing logic and memory, limiting the efficiency of the rendering process.
Innovation Solution
A hybrid rendering technique is introduced, which divides the rendering space into tiles and uses partial display lists that include identifiers of transformed primitives stored in on-chip memory, allowing for periodic retrieval and processing of primitives, reducing the need for large memory storage and minimizing bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tile-based rendering stores transformed geometry data for an entire frame in memory, then complete scene rendering is achieved, but memory bandwidth requirements increase significantly
Solution Approach 1:
The patent divides the rendering process into multiple passes, where geometry data is processed and sorted into tiles in one pass, then rendered in subsequent passes. This segmentation allows the system to work with smaller subsets of data at any given time rather than loading all transformed geometry data into memory simultaneously, thereby reducing peak memory bandwidth requirements while still achieving complete scene rendering.
Solution Approach 2:
The patent implements a preliminary geometry processing phase where primitives are transformed and sorted into tile-specific lists before the actual rasterization occurs. By performing this preliminary organization of data into manageable tile-based structures, the system prepares the geometry data in advance so that during rendering, only the relevant tile data needs to be accessed from memory, reducing the bandwidth burden during the critical rendering phase.
2Quantity of substance
If tile-based rendering divides rendering space into tiles for independent processing, then on-chip memory usage is optimized, but the complexity of managing partial display lists increases
Solution Approach 1:
The patent segments the display list into multiple partial display lists, each corresponding to a specific tile or group of tiles. This segmentation allows each partial display list to be compact and tile-specific, reducing the amount of data that needs to be held in on-chip memory at any one time. The segmentation strategy directly addresses the memory optimization goal while the systematic organization keeps management complexity manageable.
Solution Approach 2:
The patent introduces a hierarchical dimension to display list management by organizing primitives not just by tile but also by depth buffers and rendering passes. This multi-dimensional organization allows the system to manage partial display lists more efficiently by leveraging the additional organizational layers, reducing the burden on any single management structure while optimizing on-chip memory utilization.
3Loss of energy
If periodic retrieval of primitives from on-chip memory is implemented, then bandwidth requirements are minimized, but rendering throughput may be reduced
Solution Approach 1:
The patent maintains continuous useful action by overlapping geometry processing with rendering operations. While one tile is being rendered, the system continues to process geometry for subsequent tiles and prepare the next set of partial display lists. This pipelining ensures that the periodic retrieval from on-chip memory does not create idle periods, as the system is continuously productive across multiple operation stages, thereby minimizing the impact on overall rendering throughput.
Solution Approach 2:
The patent implements periodic retrieval of primitive data from on-chip memory in a structured manner, where data is fetched in regular intervals corresponding to tile completion cycles. This periodic action is synchronized with the rendering pipeline so that memory bandwidth is utilized efficiently during dedicated fetch windows rather than continuously, reducing peak bandwidth requirements while maintaining steady rendering throughput through predictable, rhythmically optimized data access patterns.
Data Source
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AI summary
Tiling engines and methods for use in a graphics processing system for hierarchically tiling a plurality of primitives. The tiling engine includes: a chain of sorting units comprising a top level sorting unit followed by one or more lower level sorting units, wherein: the top level sorting unit is configured to: determine which of a plurality of regions of a render space each of the plurality of primitives, at least partially, falls within; and for each region a primitive, at least partially, falls within, store an identifier of that primitive in a queue of the top level sorting unit that is associated with that region; and each of the one or more lower level sorting units is configured to: select one or more queues of a preceding sorting unit in the chain to process; for each of the selected queues, determine which of a plurality of sub-regions of the region associated with that queue each of the primitives identified in that queue, at least partially, falls within; and for each sub-region a primitive, at least partially, falls within, store an identifier of that primitive in a queue of the lower level sorting unit that is associated with that sub-region; and an output unit configured to output the primitives identified in the queues of the last lower level sorting unit in the chain on a queue by queue basis.