Hierarchical Tiling Engines for Predictable Graphics Memory Usage
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Solution Overview
Problem
Existing tile-based rendering (TBR) graphics processing systems face inefficiencies due to unpredictable memory usage and bandwidth requirements for tiling information, particularly when handling large primitives that cover significant portions of the rendering space, leading to potential memory overflow and suboptimal rasterization performance.
Innovation Solution
Implement a multi-level hierarchical tiling structure where tiles are grouped into successively larger non-overlapping groups, with each level having more tiles than the previous, and associate primitive blocks with these groups to generate control streams that limit the number of entries per tile group, ensuring efficient memory allocation and reduced bandwidth by fixing the maximum number of control streams each primitive block can occupy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional tile-based rendering is used to reduce memory bandwidth, then bandwidth requirements are reduced, but memory usage becomes unpredictable and may overflow when handling large primitives
Solution Approach 1:
The patent segments the rendering space into a hierarchical structure of tile groups at multiple levels. Each tile group is associated with a control stream that lists primitive blocks affecting that tile group. This segmentation allows predictable allocation of memory resources by limiting the number of control stream entries per tile group, preventing memory overflow while maintaining the bandwidth benefits of tile-based rendering.
Solution Approach 2:
The patent changes the parameter of control stream entry limits by introducing a maximum number of tile groups that can be associated with each primitive block. This parameter change transforms unpredictable memory usage into predictable memory allocation, ensuring that memory overflow cannot occur while preserving the efficiency of tile-based rendering for large primitives.
2Reliability
If primitive blocks are associated with multiple tile groups to ensure complete coverage, then rendering completeness is improved, but memory usage and data processing redundancy increase
Solution Approach 1:
The patent applies partial action by limiting the number of tile groups that can be associated with each primitive block to a predetermined maximum. This controlled limitation ensures that while rendering completeness is maintained through proper association, memory usage is prevented from becoming excessive. The system processes only the necessary control stream entries within the defined limit, reducing data processing redundancy.
3Device complexity
If a flat tile structure is used for simplicity, then device complexity is reduced, but memory allocation becomes inefficient and bandwidth is not optimized
Solution Approach 1:
The patent introduces another dimension to the tile structure by organizing tiles into hierarchical levels of tile groups. This multi-level hierarchy adds a dimensional layer to the traditional flat tile structure, enabling more efficient memory allocation and bandwidth optimization. The hierarchical organization allows the system to process and manage primitive blocks more effectively while maintaining manageable complexity through structured groupings.
Data Source
AI summary
Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.