Hierarchical Timing Model Extraction for IC Design
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Solution Overview
Problem
Extracted Timing Models (ETMs) lead to pessimistic timing results in top-level implementations of integrated circuit designs due to the inability to model hierarchy crossing path exceptions, resulting in unnecessary overwork by optimization engines and longer closure cycles.
Innovation Solution
A computer-implemented method and system for performing static timing analysis that extracts hierarchical crossing path exception information from a hierarchical design view, transfers it to a block view, and generates a timing model including additional arcs to model missing hierarchical boundary crossing exceptions, using a hierarchical context translator with port, internal pin, and through list information, allowing for top-level and block-level timing constraints generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If extracted timing models are used for top-level timing analysis, then timing analysis speed is improved, but timing result accuracy deteriorates due to pessimistic results
Solution Approach 1:
The design is divided into hierarchical blocks with extracted timing models for each block. The timing analysis is segmented into block-level detailed analysis and top-level aggregate analysis, allowing fast top-level analysis while maintaining accuracy through proper segmentation of timing paths.
Solution Approach 2:
A hierarchical context translator acts as an intermediary between the block-level detailed timing information and top-level timing analysis. It translates and aggregates timing data from lower levels while preserving critical timing characteristics, eliminating pessimism without sacrificing analysis speed.
2Device complexity
If hierarchical crossing path exceptions are not modeled, then device complexity is reduced, but timing analysis reliability deteriorates
Solution Approach 1:
Hierarchical crossing path exceptions are identified and modeled in advance during the block-level timing analysis phase. The exceptions are captured in the extracted timing models before top-level analysis, ensuring reliability without adding complexity during top-level analysis.
Solution Approach 2:
The timing model parameters are enhanced to include hierarchical crossing path exception information. By changing the parameters of the extracted timing models to incorporate exception data, the system maintains reliability while avoiding the need for complex additional modeling structures.
3Reliability
If pessimistic timing results are produced, then timing analysis completeness is improved, but productivity deteriorates due to unnecessary overwork and longer closure cycles
Solution Approach 1:
The timing model extraction process is made dynamic and adaptive. The system automatically adjusts the level of detail and exception modeling based on the specific design characteristics and hierarchical structure, producing accurate but not excessively conservative results that optimize closure cycle efficiency.
Solution Approach 2:
The timing analysis system incorporates feedback loops where timing results from initial analysis are used to refine the extracted timing models. This feedback mechanism eliminates pessimism iteratively while maintaining completeness, reducing unnecessary rework and improving overall productivity.
Data Source
AI summary
The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and extracting a timing model based upon, at least in part, the hierarchical crossing path exception information. Embodiments may also include implementing the timing model at a top-level view associated with the electronic design.