Hierarchical Timing Model for IC Design Clock Data Path Budgeting
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Solution Overview
Problem
Integrated circuit design complexity, particularly in giga gate scale designs, is hindered by the challenge of simultaneously timing budgeting both clock and data paths, with existing methods often overlooking clock path timing, leading to inefficiencies and prolonged design cycles.
Innovation Solution
A new timing model that considers clock path delays, allowing for independent but parallel timing analysis between blocks and the top level of the chip, enabling simultaneous time budgeting of clock and data paths to ensure accurate timing closure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing timing budgeting methods are used that overlook clock path timing, then data path timing can be analyzed, but clock path timing delays are not captured leading to inaccurate timing closure
Solution Approach 1:
The patent merges clock path timing analysis with data path timing analysis into a unified timing budgeting process. The timing model simultaneously captures both clock and data path delays, eliminating the need for separate analysis passes and ensuring comprehensive timing closure accuracy.
Solution Approach 2:
The timing model segments the analysis into distinct clock path components and data path components, allowing each to be analyzed with appropriate methodology while maintaining their interrelationships. This segmentation enables precise measurement of each path type without overwhelming complexity.
2Device complexity
If hierarchical design partitioning is implemented to manage giga gate scale complexity, then design organization is improved, but timing analysis across partitions becomes more complex and time-consuming
Solution Approach 1:
The timing model performs preliminary timing budgeting at the partition level before final integration, establishing timing constraints and budgets for each hierarchical block in advance. This preliminary action prevents timing issues from propagating through the entire design and reduces the time needed for final timing closure.
Solution Approach 2:
The patent implements nested timing analysis where timing budgets are established at multiple hierarchical levels simultaneously. Each partition contains its own timing model that is nested within the overall chip-level timing model, allowing parallel analysis across hierarchical levels and reducing total analysis time.
3Reliability
If sequential timing analysis is used to ensure accuracy, then timing closure is reliable, but design turnaround time is prolonged due to iterative processes
Solution Approach 1:
The timing model enables continuous timing analysis across all hierarchical levels simultaneously, rather than requiring sequential passes. The parallel evaluation of clock and data paths maintains timing closure reliability while eliminating iterative wait states, thereby accelerating design turnaround.
Solution Approach 2:
The system implements feedback mechanisms where timing violations detected at any hierarchical level immediately trigger localized adjustments without requiring full re-analysis of the entire design. This feedback loop maintains timing closure reliability while minimizing the impact on overall design productivity.
Data Source
AI summary
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.