Hierarchical Circuit Verification Across Tool Version Mismatches
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Solution Overview
Problem
The challenges of static verification in large SoC designs include high runtime and storage requirements in full-flat verification, and version compatibility issues in abstract model hierarchical flow.
Innovation Solution
A method and system for generating and regenerating abstract models of circuit blocks using version-specific setup information to ensure compatibility with the verification tool version used for top-level SoC verification, enabling parallel regeneration and push-button hierarchical flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full-flat verification is used to verify large SoC designs, then verification coverage is improved, but runtime and storage space requirements increase significantly
Solution Approach 1:
The patent divides the large SoC design into multiple hierarchical blocks, each with its own abstract model. Instead of verifying the entire design in a single flat level, the verification is segmented into block-level verifications using abstract models and top-level verification, reducing the runtime burden while maintaining verification coverage.
Solution Approach 2:
The patent introduces abstract models as intermediary representations between the detailed block-level designs and the top-level system verification. These abstract models serve as mediators that capture essential behavioral characteristics without requiring full detailed verification at the top level, thus reducing runtime while preserving verification effectiveness.
2Productivity
If abstract model hierarchical flow is used to reduce runtime, then verification efficiency is improved, but version compatibility issues arise between different tool versions
Solution Approach 1:
The patent changes the parameter representation by capturing not just the abstract model structure but also the specific tool version parameters used to generate each abstract model. This allows the verification system to adapt to different tool versions by tracking and managing version-specific parameters, enabling seamless integration of abstract models generated by different verification tool versions.
Solution Approach 2:
The patent creates a universal abstract model representation that can accommodate multiple tool versions. The abstract model structure is designed to be version-agnostic while storing version-specific metadata, allowing the same verification framework to work with abstract models generated by different verification tool versions, thus achieving multi-functionality across version boundaries.
3Measurement precision
If abstract models are regenerated to ensure version compatibility, then verification accuracy is improved, but additional processing time is required
Solution Approach 1:
The patent performs preliminary version compatibility checking before verification to determine whether abstract models need regeneration. By checking version compatibility in advance, the system can avoid unnecessary regeneration operations and only regenerate abstract models when actually required, thus maintaining verification accuracy while minimizing additional processing time.
Solution Approach 2:
The verification system automatically detects version incompatibilities and triggers regeneration of abstract models without manual intervention. The system self-manages the regeneration process by identifying which abstract models need updating and executing regeneration only for those specific models, reducing overall processing time compared to manual regeneration approaches.
Data Source
AI summary
A method of performing static verification of a circuit design that includes a number of circuit blocks, includes, in part, receiving a first model of a first block generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a multitude of verification tests performed by the first version of the tool as well as associated first setup information. In response to the determination that, for each of the of tests performed, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design are regenerated.