Hierarchical VLIW Packet Decoding for Cache Size Reduction

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Solution Overview

Problem

Current computing devices face inefficiencies in instruction processing due to limited instruction cache size and energy consumption from frequent code fetching, as they lack effective methods to pack instructions densely.

Innovation Solution

The method involves receiving and decoding instruction packets to identify single instructions or sub-packets, routing these sub-instructions to specific execution units for concurrent execution, thereby increasing instruction density and reducing cache size requirements and energy usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of stationary object

If instructions are packed densely in instruction packets, then instruction cache size can be reduced, but instruction decoding and processing complexity increases

Engineering Contradiction:
Improveinstruction cache sizeVSAvoidinstruction decoding complexity
Core Design Contradiction:
Volume of stationary objectVSDevice complexity

Solution Approach 1:

The instruction packet is segmented into multiple instruction fields, where each field can contain either a standard instruction or a sub-packet instruction. This segmentation allows the decoder to process each field independently and identify sub-packet instructions through specific parse values, reducing the overall decoding complexity while maintaining dense packing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Sub-packets are nested within the instruction packet structure, where a sub-packet instruction field contains multiple sub-instructions that are further nested. This nested structure enables efficient space utilization in the instruction cache while the hierarchical decoding approach (first level for main instructions, second level for sub-instructions) manages the complexity through staged processing.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Volume of stationary object

If more instructions are stored in the same cache space, then instruction cache size is reduced, but energy consumption for code fetching increases

Engineering Contradiction:
Improveinstruction cache sizeVSAvoidenergy consumption for code fetching
Core Design Contradiction:
Volume of stationary objectVSUse of energy by moving object

Solution Approach 1:

By segmenting the instruction packet into multiple instruction fields with clear parse values, the system can efficiently pack more instructions into the same cache space. This increased density reduces the number of cache lines that need to be fetched from memory, thereby reducing the total energy consumption for code fetching despite the increased instruction count per packet.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If sub-packets with multiple sub-instructions are implemented, then instruction density increases, but processing and routing complexity increases

Engineering Contradiction:
Improveinstruction densityVSAvoidprocessing and routing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The instruction packet is divided into distinct instruction fields, each with a parse value that identifies whether it contains a standard instruction or a sub-packet instruction. This segmentation allows execution units to process instructions in a standardized manner while the parse values provide simple routing logic, reducing processing complexity despite increased instruction density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The instruction fields serve multiple functions: they can contain standard instructions for direct execution or sub-packet instructions that expand into multiple sub-instructions. This multi-functionality is achieved through a unified packet structure with parse values that guide the execution units, simplifying the routing logic while maintaining high instruction density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9678754B2System and method of processing hierarchical very long instruction packets
Publication Date: 2017.06.13 QUALCOMM INC
  • US9678754B2 patent drawing
  • US9678754B2 patent drawing
  • US9678754B2 patent drawing

AI summary

A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.