Hierarchy-Aware Integrated Circuit Layout Overlays for Congestion
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Solution Overview
Problem
Traditional layout electronic design automation (EDA) tools lack a hierarchy-aware approach, leading to integration problems and congestion issues in integrated circuit design, particularly in multi-occurrence cells where sub-blocks obstruct critical signals and require manual, sequential design edits.
Innovation Solution
A hierarchy-aware integrated circuit layout tool generates an overlay that projects higher-level objects overlapping with current cells, providing an abstraction and guidance for layout designers to avoid congestion and facilitate parallel design by multiple users.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional layout EDA tools are used without hierarchy-aware approach, then the design process is simpler to operate, but integration problems and congestion issues arise in multi-occurrence cells
Solution Approach 1:
The system performs preliminary action by projecting higher-level hierarchy objects onto lower-level cells before final layout completion. This allows designers to predict and prevent congestion issues in advance by visualizing potential conflicts between sub-blocks and critical signals at higher levels, thereby improving integration reliability without requiring complex real-time adjustments during the design process.
Solution Approach 2:
The overlay projection acts as an intermediary mechanism that mediates between different hierarchy levels. By superimposing higher-level objects onto lower-level cell views, the system provides visual context about potential conflicts without requiring designers to manually navigate through multiple hierarchy levels, thus improving reliability while maintaining operational simplicity.
2Manufacturing precision
If manual sequential design edits are performed for sub-blocks, then design precision can be maintained, but design time and productivity are reduced
Solution Approach 1:
The system provides immediate feedback by visually projecting higher-level objects onto lower-level cells, allowing designers to see the impact of their placement decisions in real-time. This feedback mechanism enables precise layout adjustments without requiring sequential manual edits, as designers can quickly identify and resolve conflicts while maintaining high productivity through parallel design operations.
Solution Approach 2:
By performing preliminary projection of higher-level objects, the system allows designers to plan and adjust layouts in advance, avoiding the need for time-consuming sequential edits. Designers can make precise adjustments to sub-blocks while being aware of potential conflicts, thereby maintaining both precision and productivity.
3Ease of manufacture
If sub-blocks are designed in isolation, then ease of manufacture is improved, but congestion issues and integration problems increase
Solution Approach 1:
The system adds a visual dimension by projecting higher-level hierarchy objects onto lower-level cell views. This dimensional overlay allows sub-blocks to be designed with the simplicity of isolated design while simultaneously revealing potential congestion issues and interference patterns with higher-level structures, thus maintaining ease of manufacture while reducing harmful integration effects.
Solution Approach 2:
The overlay projection serves as an intermediary that connects isolated sub-block design with overall integration concerns. It provides visual context about potential conflicts without complicating the sub-block design process itself, allowing designers to maintain design simplicity while being aware of and able to resolve integration issues.
Data Source
AI summary
In an approach, a processor identifies a current cell depicted in an integrated circuit layout tool, the current cell of a hierarchical layout comprises a plurality of cells. A processor generates an overlay, the overlay comprising an abstraction of at least one object present in a higher level of the hierarchical layout that overlaps with the current cell. A processor projects the overlay onto the current cell.