High Bandwidth DIMM Splitting Data Bus for Concurrent Rank Access
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Solution Overview
Problem
Current memory channel implementations face challenges in increasing bandwidth while maintaining low power consumption, as multi-drop configurations on memory channels limit the number of ranks of memory chips that can be effectively used, leading to performance bottlenecks.
Innovation Solution
The introduction of a high bandwidth DIMM design that splits the data bus into two separate channels, allowing concurrent data transfers between multiple ranks on each channel, and utilizing buffer circuitry to perform 2:1 multiplexing, enabling simultaneous data access across all ranks within a single time window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple ranks of memory chips are connected in a multi-drop configuration on a memory channel, then memory channel capacity increases, but signal loading increases and timing margins deteriorate
Solution Approach 1:
The patent divides the memory channel into two separate sub-channels (first and second sub-channels), each handling a portion of the memory ranks. This segmentation reduces the number of drops per sub-channel, thereby reducing signal loading and improving timing margins while maintaining the ability to access multiple ranks concurrently.
Solution Approach 2:
The patent introduces buffer circuitry as an intermediary component between the memory controller and the memory chips. The buffers act as mediators that manage data flow and timing, allowing multiple ranks to be accessed simultaneously without degrading signal integrity or timing margins on each sub-channel.
2Speed
If memory speed is increased to improve system performance, then bandwidth increases, but power consumption increases
Solution Approach 1:
By splitting the memory channel into two sub-channels, the patent enables more efficient data flow management. Each sub-channel can operate at optimized speeds with reduced contention, improving overall memory speed and bandwidth while the distributed architecture prevents excessive power concentration in a single channel.
Solution Approach 2:
The patent enables concurrent data transfers across multiple ranks simultaneously through the two sub-channels. This continuous parallel operation maximizes memory bandwidth utilization, allowing the system to achieve high performance without needing to increase the speed of individual channels to unsustainable levels, thereby controlling power consumption.
3Quantity of substance
If the number of memory chips per DIMM is increased to boost capacity, then memory channel loading increases, but bandwidth per channel is limited
Solution Approach 1:
The patent distributes memory chips across two separate sub-channels, organizing them into multiple ranks that can be accessed concurrently. This segmentation allows the DIMM to support higher total capacity while each sub-channel maintains manageable loading, thereby preserving bandwidth per channel while increasing overall productivity.
Solution Approach 2:
The patent transitions from a single-dimensional memory channel architecture to a two-dimensional architecture with parallel sub-channels. This dimensional change enables simultaneous data transfers across multiple ranks, effectively multiplying the bandwidth capacity without increasing the loading on any single channel beyond acceptable limits.
Data Source
AI summary
A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.