High-Bandwidth Extended Memory for Parallel GPU Processing

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Solution Overview

Problem

Existing parallel processing systems face challenges in accessing extended memory due to limited high-bandwidth memory availability, leading to reduced performance when executing threads that require large memory spaces, and existing solutions incur bandwidth penalties or reduce memory availability on other GPUs.

Innovation Solution

A method for accessing extended memory in a parallel processing system by directing memory accesses through a memory controller associated with the central processing unit, bypassing system memory management units, and utilizing a high-speed chip-to-chip interface to access a portion of system memory as extended GPU memory (EGM), which is managed by the operating system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is paged in and out from system memory to GPU local memory, then threads can access large memory spaces, but GPU performance is significantly reduced due to low bandwidth

Engineering Contradiction:
Improvememory capacityVSAvoidGPU performance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent merges system memory with GPU local memory to create a unified high-bandwidth memory space. The GPU can access both its local high-bandwidth memory and the CPU's system memory through the same high-speed interconnect, eliminating the need to page data through low-bandwidth system memory interfaces. This allows threads to access large memory capacities while maintaining high bandwidth performance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes system memory accessible to the GPU through the high-speed interconnect, allowing the same memory resource to serve both CPU and GPU needs. The system memory can be used as extended GPU memory without requiring separate memory resources, enabling the GPU to access large datasets while the CPU continues to use the same memory space for its operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If a GPU is allocated memory from another GPU via high-speed bus, then high-bandwidth memory capacity increases, but the allocating GPU's available memory is reduced

Engineering Contradiction:
Improvehigh-bandwidth memory capacityVSAvoidmemory availability
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent makes system memory universally accessible to multiple GPUs through the high-speed interconnect. Instead of allocating memory from one GPU to another (which reduces the source GPU's availability), the system allows each GPU to access the shared system memory space independently, maintaining full availability for each GPU while providing extended memory capacity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If IOMMU translation is used for direct system memory access, then memory management is simplified, but access bandwidth is reduced

Engineering Contradiction:
Improvememory managementVSAvoidmemory access bandwidth
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent extracts the IOMMU translation step from the memory access path by allowing the GPU to directly access system memory through the high-speed interconnect without requiring address translation. The GPU's address space is directly mapped to the system memory physical addresses, eliminating the translation overhead and associated bandwidth reduction while maintaining simplified memory management through the unified address space.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12443363B2High bandwidth extended memory in a parallel processing system
Publication Date: 2025.10.14 NVIDIA CORP
  • US12443363B2 patent drawing
  • US12443363B2 patent drawing
  • US12443363B2 patent drawing

AI summary

Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.