High-Bandwidth NAND Memory With Always-On Bit Lines
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Solution Overview
Problem
Conventional NAND memory devices suffer from low bandwidth and high power consumption, making them unsuitable alternatives to high bandwidth memory (HBM) for applications requiring high data rates and low power consumption, such as machine learning with large language models.
Innovation Solution
Implement a method where bit lines in NAND memory devices remain at an elevated voltage during and between read operations, allowing multiple read operations to be performed without ramping down, thereby increasing bandwidth and reducing read time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional NAND memory devices are used, then cost is reduced compared to HBM, but bandwidth is too low and power consumption is too high
Solution Approach 1:
The bit lines are pre-charged to a first voltage level before read operations, and this elevated voltage state is maintained throughout the read operation and between sequential read operations. This preliminary voltage establishment eliminates the need to recharge bit lines between operations, thereby increasing bandwidth while managing power consumption through optimized voltage timing.
2Loss of time
If bit lines are ramped down between read operations, then power consumption is reduced, but read time increases due to voltage ramping overhead
Solution Approach 1:
The bit lines maintain a continuous elevated voltage state throughout the read operation and between sequential read operations, eliminating interruptions for voltage ramping. This continuous voltage maintenance enables faster sequential reads by avoiding the time-consuming voltage transition cycles, thereby reducing read time while the controller manages power consumption through selective voltage maintenance.
Data Source
AI summary
The memory device includes a plane with a plurality of memory blocks that are in electrical communication with a set of bit lines. The memory device also includes circuitry which is in communication with the plurality of memory blocks. The circuitry is configured to perform a first read operation on a first memory block of the plurality of memory blocks while the bit lines of the set of bit lines are held at a first voltage that is greater than zero Volts. Without ramping the bit lines of the set of bit lines down from the first voltage, the circuitry is also configured to perform a second read operation on a second memory block of the plurality of memory blocks while the bit lines of the set of bit lines are held at the first voltage.