High Capacity I/O Cells for Wafer-Level Stress Testing
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Solution Overview
Problem
Traditional burn-in testing of packaged semiconductor devices is costly due to the need to discard entire packages when defects are found, and conventional probe test setups are inadequate for high power die during massively parallel wafer-level stress testing.
Innovation Solution
Integration of high capacity I/O cells into the power distribution grid of each die, featuring a larger contact pad over metal lines with oxide pillars for reinforcement, allowing for high voltage and current handling and reducing the number of probe pins needed, thus enabling cost-effective massively parallel wafer-level stress testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If package-level burn-in testing is performed on packaged semiconductor devices, then defects can be detected, but fabrication costs increase due to discarding entire defective packages
Solution Approach 1:
The patent performs wafer-level stress testing before packaging, allowing defects to be detected and defective die to be discarded early in the fabrication process. This preliminary action prevents the need to package and then discard entire defective packages, thereby reducing fabrication costs while maintaining defect detection capability
Solution Approach 2:
The patent segments the testing process from the packaged device level to the wafer/die level. By testing individual die on the wafer before packaging, the system can identify and discard only the defective die rather than entire packages, reducing material waste and fabrication costs
2Productivity
If conventional probe test setups are used for wafer-level stress testing, then testing can be performed, but high power requirements cannot be met for massively parallel testing
Solution Approach 1:
The high capacity I/O cells are designed to serve multiple functions: they act as power pads during wafer-level stress testing to handle high voltage and current, and then serve as signal pads for the final packaged device. This multi-functionality enables massively parallel testing with high power requirements while maintaining compatibility with the final product specifications
Solution Approach 2:
The patent changes the electrical parameters of the I/O cells by configuring them with larger contact pads and multiple underlying metal lines capable of handling high voltage and current during testing. After testing, these same cells operate at standard electrical parameters for signal transmission in the final device, allowing the system to meet high power requirements during testing without compromising final device performance
3Power
If high capacity I/O cells with larger contact pads are used, then high voltage and current can be handled, but the structure requires reinforcement to prevent damage
Solution Approach 1:
The high capacity I/O cell structure combines multiple materials and layers: a large contact pad surface, multiple underlying metal lines (first and second metal layers) for current carrying, and dielectric material between the layers. This composite structure provides both the electrical capacity for high voltage and current handling and the structural integrity needed to prevent damage during probing and operation
Data Source
AI summary
A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.