High Carbon Masking Structures for Fine Semiconductor Patterning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current double and reverse patterning technologies for integrated circuit fabrication face challenges such as high production costs, long processing times, and void formation in high aspect ratio openings, which limit the achievement of fine pitch patterns.
Innovation Solution
The method involves forming first and second masking structures from high carbon content materials using spin-coating and heating processes, with a buffer layer and hard mask layers to pattern semiconductor substrates, allowing for the creation of patterns with twice the pitch of traditional photolithography while avoiding voids in high aspect ratio openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technology using spacers is used, then smaller IC dimensions can be achieved, but production cost increases and production time increases
Solution Approach 1:
The patent applies preliminary action by forming a buffer layer on the sidewalls of mandrels before depositing the second photoresist material. This buffer layer pre-prepares the surface for subsequent patterning steps, enabling better adhesion and pattern definition while simplifying the overall process compared to traditional spacer-based double patterning
Solution Approach 2:
The patent uses photoresist structures as templates or copies to define the final pattern. By forming first and second photoresist patterns that are subsequently removed, the desired fine pitch pattern is transferred to the target layer without requiring complex spacer formation and removal steps
2Manufacturing precision
If double patterning technology using spacers is used, then smaller IC dimensions can be achieved, but void formation occurs in high aspect ratio openings
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the mandrel sidewalls and the second photoresist material. This buffer layer mediates the interface, preventing direct contact that would cause void formation in high aspect ratio openings while still enabling precise pattern transfer
Solution Approach 2:
The patent uses disposable photoresist structures (first and second photoresist patterns) that are formed temporarily to define the pattern and are subsequently removed. These temporary structures enable precise patterning without creating permanent voids in the final device structure
3Ease of manufacture
If traditional photolithography is used, then production cost is lower, but line resolution is limited by large photo-resist molecule size
Solution Approach 1:
The patent segments the patterning process into multiple steps with different photoresist materials applied sequentially. By using separate first and second photoresist patterns with different molecular sizes and properties, the process achieves finer line resolution than single-step photolithography while maintaining cost effectiveness
Solution Approach 2:
The patent changes parameters by using different photoresist materials with varying molecular sizes, viscosities, and etch selectivities for different patterning steps. This allows optimization of line resolution for each step while controlling overall production cost
4Ease of manufacture
If photo-resist material with large polymer molecules is used, then ease of manufacture is maintained, but line edge roughness increases
Solution Approach 1:
The patent applies local quality by using different photoresist materials with different molecular sizes and properties in different locations or steps of the patterning process. The first photoresist material may have larger molecules for ease of manufacture, while the second uses materials optimized for smooth line edges
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the patterning of integrated circuits with small dimensions at a lower cost and reduced void formation, achieving finer pitches than traditional photolithography while maintaining efficient processing.
Implementation Method 1
heating the organic compound material at a temperature of from about 300° Celsius to about 550° Celsius for from about 30 seconds to about 300 seconds to form a hardened organic compound layer
Implementation Method 2
spin-coating an organic compound material over a semiconductor substrate
Data Source
AI summary
For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.