High Charge Density Dielectric Layer for FET Scaling
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Solution Overview
Problem
As field effect transistors (FETs) are scaled to shorter channel lengths, they experience diminishing threshold voltage, scattering, and reduced electron mobility due to charge entering the substrate from overlying dielectric layers, impairing device performance and making it difficult to design integrated circuits.
Innovation Solution
A high charge density dielectric layer is formed using a high-k dielectric material doped with a metal dopant layer, which is thermally annealed to create electric dipoles that are separated from the substrate by a lower dielectric layer, preventing deleterious transport effects and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FET channel length is decreased to enable further scaling, then device density and integration capability are improved, but threshold voltage control deteriorates and short channel effects increase
Solution Approach 1:
A charge density dielectric layer is introduced as an intermediary element between the gate electrode and the substrate. This intermediate layer modifies the electric field distribution in the channel region, providing better threshold voltage control and reducing short channel effects while enabling further device scaling and higher density integration
2Productivity
If FET is scaled to shorter channel lengths, then device density is improved, but electron mobility is reduced due to scattering
Solution Approach 1:
The charge density dielectric layer acts as a mediator that modifies the electric field profile in the channel, reducing scattering effects on charge carriers. By controlling the field distribution, it maintains higher electron mobility even at scaled dimensions, thus preserving device speed while enabling higher density
3Reliability
If charge is placed closer to the substrate to enhance threshold voltage control, then VT control is improved, but scattering and mobility reduction increase
Solution Approach 1:
The charge density dielectric layer introduces localized charge distribution at specific positions within the gate stack. By carefully controlling the charge location and density, it provides effective threshold voltage control while minimizing the adverse effects of scattering and mobility reduction that would occur with uniform or poorly positioned charge
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in improved short channel effect characteristics, allowing for shorter gate lengths, lower capacitance, higher performance, and lower power consumption by preventing scattering and mobility reduction, thus overcoming the limitations of conventional devices.
Implementation Method 1
thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles
Implementation Method 2
The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material
Implementation Method 3
The electric dipoles are separated from the substrate by the lower dielectric material
Data Source
AI summary
Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density dielectric layer is formed with thermal annealing-induced electric dipoles at locations corresponding to the selectively patterned dopant material.