High-CMTI Isolator Link Using a Tapped Impedance Path
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional on-chip isolator devices face a trade-off between high common-mode transient immunity (CMTI) and gain, and are ill-suited for high-power applications due to incompatibility with semiconductor processes used for large wafers, particularly when using materials like polyimide for isolation barriers.
Innovation Solution
The design incorporates a first die with an isolation barrier and a second barrierless die with a tapped impedance element, coupled via electrical connections, to enhance CMTI without sacrificing gain, allowing high-current operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an isolation barrier with materials like polyimide is used in on-chip isolator devices, then galvanic isolation and data integrity are improved, but compatibility with semiconductor processes for large wafers deteriorates and high-power applications become impossible
Solution Approach 1:
The isolator device is divided into two separate dies: a first die containing the isolation barrier and primary side circuitry, and a second barrierless die containing the secondary side circuitry. This segmentation allows each die to be optimized for its specific function - the first die maintains galvanic isolation while the second die is compatible with high-power semiconductor processes
Solution Approach 2:
A tapped impedance element is introduced as an intermediary component between the isolated primary side and the barrierless secondary side. This impedance element provides a controlled interface that maintains isolation while enabling high-power signal transmission and common-mode transient discharge
2Ease of manufacture
If conventional on-chip isolator designs are used, then manufacturing simplicity is maintained, but common-mode transient immunity deteriorates when isolation barriers are removed for high-power applications
Solution Approach 1:
The tapped impedance element serves as a mediator that provides a discharge path for common-mode transients. The tap connection to a reference potential creates a controlled impedance pathway that dissipates transient energy while maintaining the barrierless design for high-power compatibility
Solution Approach 2:
The impedance element's tapped configuration changes the electrical parameters of the secondary side, creating specific impedance characteristics that enhance common-mode transient immunity. The tap position and impedance value are optimized to provide effective transient discharge while maintaining signal integrity
3Power
If a barrierless second die is used for high-power applications, then semiconductor process compatibility and high-current operation are improved, but common-mode transient immunity deteriorates without an isolation barrier
Solution Approach 1:
The tapped impedance element acts as an intermediary protective mechanism on the barrierless die. It provides a controlled discharge path for common-mode transients without requiring an physical isolation barrier, thus maintaining both high-power capability and transient immunity
Solution Approach 2:
The isolation barrier material is extracted from the second die to enable high-power semiconductor processes, while the protective function against common-mode transients is extracted and implemented through the tapped impedance element instead
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The isolator device achieves CMTI exceeding 100 kV/μs while maintaining high gain, suitable for high-power applications such as motor drivers, by providing a discharge path for common-mode transients through the tapped impedance element.
Implementation Method 1
The second die is provided with a tapped impedance element, an impedance element having a tap that couples the impedance element to a reference potential (e.g., to ground). The secondary side of the isolator of the first die is coupled to the tapped impedance element of the second die, thus creating a discharge path for common-mode transients.
Data Source
AI summary
Described herein are on-chip isolator devices that can be employed in high-power applications and that are designed to enhance high common-mode transient immunity (CMTI) without sacrificing isolator gain. An isolator device includes two dies. A first die supports an isolation barrier and the second die is barrierless. The second die is barrierless in that it lacks isolation materials that are commonly used to sustain isolation barriers in on-chip isolator devices (e.g., polyimide). To enhance CMTI despite the absence of a further isolation barrier formed on the second die, the second die is provided with a tapped impedance element, an impedance element having a tap that couples the impedance element to a reference potential (e.g., to ground). The secondary side of the isolator of the first die is coupled to the tapped impedance element of the second die, thus creating a discharge path for common-mode transients.