High Confidence Multiple Branch Offset Predictor for BPU Bandwidth
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Solution Overview
Problem
Conventional branch prediction units (BPUs) in processors face limitations in bandwidth and performance due to frequent re-steering events caused by taken branches, which restrict the sustained instruction bandwidth and overall processor performance, especially in wide and deep out-of-order cores.
Innovation Solution
The High Confidence Multiple Branch (HCoMB) offset predictor identifies and predicts multiple taken branches, allowing direct jumping to their targets, reducing re-steering events and enhancing BPU bandwidth by utilizing the Program Counter and branch history to predict the next N taken branches and their targets, thereby increasing the Front-End bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional branch prediction units are used, then single branch prediction is provided, but re-steering events occur frequently causing bandwidth limitations
Solution Approach 1:
The patent segments the branch prediction task by separating taken branch prediction from not-taken branch prediction using two distinct data structures (first data structure for taken branches, second data structure for not-taken branches). This segmentation allows the predictor to efficiently handle multiple taken branches simultaneously without triggering re-steering events, thereby increasing BPU bandwidth and reducing prediction time.
2Productivity
If multiple taken branches are predicted, then re-steering events are reduced, but device complexity increases
Solution Approach 1:
The patent implements dynamic selection between two data structures based on branch type (taken vs. not-taken). The system dynamically routes branch predictions to the appropriate data structure, enabling flexible handling of multiple taken branches while maintaining manageable complexity through conditional logic rather than rigid structural expansion.
Solution Approach 2:
The patent changes the parameter of branch prediction by introducing a confidence level parameter and using different data structures for different branch outcomes. This parameter-based approach allows the system to adapt its prediction strategy based on the specific branch characteristics, improving instruction bandwidth without proportionally increasing complexity.
3Measurement precision
If branch history is utilized for prediction, then prediction accuracy improves, but storage requirements increase
Solution Approach 1:
The patent extracts only the necessary branch history information needed for prediction into compact data structures. By taking out only the relevant historical data (branch outcomes and targets) and storing them in optimized formats, the system achieves high prediction accuracy while minimizing storage capacity requirements.
Solution Approach 2:
The patent applies partial action by maintaining branch history for only the most recent and relevant branches rather than all historical branches. This selective approach provides sufficient prediction accuracy for improving instruction bandwidth while keeping storage requirements manageable through focused history tracking.
Data Source
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AI summary
An embodiment of an integrated circuit may comprise a front end unit, and circuitry coupled to the front end unit, the circuitry to provide a high confidence, multiple branch offset predictor. For example, the circuitry may be configured to identify an entry in a multiple-taken-branch prediction table that corresponds to a conditional branch instruction, determine if a confidence level of the entry exceeds a threshold confidence level, and, if so determined, provide multiple taken branch predictions that stem from the conditional branch instruction from the entry in the multiple-taken-branch prediction table. Other embodiments are disclosed and claimed.