Semiconductor Package Layout Using High-CTE Mold Layer Against Warpage
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Solution Overview
Problem
Semiconductor packages face challenges in controlling warpage due to structural imbalances between metal interconnection lines and through-electrodes, affecting reliability and performance.
Innovation Solution
A semiconductor package design incorporating an upper substrate with a mold layer made of insulating material with a higher coefficient of thermal expansion than the substrate, along with a buffer layer and through-electrodes, to reduce warpage and enhance reliability by adjusting thermal expansion and stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal interconnection lines and through-electrodes are used to electrically connect semiconductor chips to PCB, then electrical connectivity is achieved, but structural imbalance causes warpage
Solution Approach 1:
The patent changes the physical parameters of the mold layer by selecting materials with specific coefficients of thermal expansion that are greater than both the upper substrate and the lower substrate. This parameter change allows the mold layer to compensate for structural imbalances and control warpage while maintaining electrical connectivity through the through-electrodes and interconnection lines.
Solution Approach 2:
The patent employs composite material structure by using a mold layer composed of insulating material with differentiated thermal expansion properties relative to the substrate layers. This composite approach creates a balanced structure that simultaneously provides electrical connectivity and prevents warpage through the synergistic interaction of materials with different thermal characteristics.
2Shape
If mold layer with higher coefficient of thermal expansion than upper substrate is used, then warpage is controlled, but stress distribution must be optimized
Solution Approach 1:
The patent optimizes stress distribution by carefully selecting the coefficient of thermal expansion parameter of the mold layer material. By setting this parameter greater than both the upper substrate and lower substrate, the mold layer expands more during thermal cycling, creating a compensating effect that reduces warpage while distributing stress uniformly across the package structure.
3Reliability
If multiple layers including buffer layer and mold layer are added to control warpage, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses composite material layers (buffer layer and mold layer with specific thermal expansion properties) to achieve warpage control and improved reliability. The composite structure, while adding layers, uses materials with coordinated thermal properties that work together to stabilize the package, making the complexity manageable through material property coordination rather than arbitrary structural additions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively controls warpage and improves the reliability of semiconductor packages by adjusting thermal expansion and reducing stress on bumps, ensuring stable performance.
Implementation Method 1
The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate
Data Source
AI summary
A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.