High-Density Connection Layer Packaging for Thinner Flip-Chip Substrates
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Solution Overview
Problem
Existing flip chip packaging methods require numerous substrate layers, leading to complex layout and wiring difficulties, reduced integration levels, and increased costs, which are not suitable for high-density packaging needs.
Innovation Solution
A method for chip packaging that replaces part of the substrate's wiring layer with a high-density connection layer, comprising a multilayered metal wiring layer and plastic sealing layers, embedded within the substrate, and uses a wafer-level process to simplify the production process and reduce substrate layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more substrate layers are used to meet high-density packaging requirements, then the number of lines and pins can be increased, but the layout and wiring difficulty increases and integration level decreases
Solution Approach 1:
The patent merges the substrate wiring function with a separate high-density connection layer. Instead of increasing substrate layers, the invention combines traditional substrate wiring with an additional connection layer that provides high-density interconnections, thereby increasing the number of lines and pins without proportionally increasing substrate complexity
Solution Approach 2:
The patent transitions from two-dimensional substrate wiring to three-dimensional interconnection by stacking multiple connection layers (first connection layer, second connection layer) above the substrate. This vertical dimensionality allows more connection paths without increasing the substrate's horizontal complexity
2Productivity
If more substrate layers are used to achieve high-density packaging, then circuit integration can be improved, but the production process becomes more complex
Solution Approach 1:
The patent segments the interconnection function into separate modules: the substrate provides mechanical support and basic wiring, while distinct connection layers (first connection layer with first conductive patterns, second connection layer with second conductive patterns) provide high-density electrical connections. This segmentation allows each component to be optimized independently, simplifying the overall manufacturing process
Solution Approach 2:
The patent performs preliminary actions by pre-forming the high-density connection layers with their conductive patterns before final assembly. The first connection layer and second connection layer are prepared in advance with their respective conductive patterns, allowing for standardized manufacturing processes and reducing on-site complexity
3Quantity of substance
If more substrate layers are used for high-density packaging, then the number of connections can be increased, but costs increase
Solution Approach 1:
The patent creates a universal connection structure where the first connection layer and second connection layer can serve multiple functions: electrical interconnection, mechanical support, and signal routing. This multi-functionality reduces the need for additional specialized components, thereby increasing the number of connections without proportionally increasing manufacturing cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances integration and performance by reducing substrate thickness and complexity, allowing for more compact device arrangement and lower production costs, while improving connection efficiency and design flexibility.
Implementation Method 1
forming said multilayered metal wiring layer by electroplating or sputtering process within the openings
Implementation Method 2
forming said multilayered metal wiring layer by electroplating or sputtering process within the openings
Data Source
AI summary
Disclosed are a method for chip packaging having a high-density connection layer and a chip packaging structure, the method comprising S1: preparing a high-density connection layer having multilayered metal wiring layer; S2: preparing a substrate intermediate, and attaching thereto the high-density connection layer; S3: embedding the high-density connection layer into the substrate and preparing a first type pads connected with the multilayered metal wiring layer and a second type pads connected with a wiring layer of the substrate intermediate; S4: inversely mounting the chip on the substrate surface, the first type chip bumps being connected to the first type pads, and the second type chip bumps being connected to the second type pads. Part of the wiring layer inside the substrate is replaced with single-sided or double-sided high-density connection layer to reduce the number of layers and thickness of the substrate, facilitating layout and wiring and improving integration and performance.