High Density Etch-Stop Layer for Via Formation
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Solution Overview
Problem
High density integrated circuits face defects due to misalignment and over-etching during the formation of vias in low-k dielectric layers, which can be attributed to the lack of effective etch stop layers with sufficient etch resistance.
Innovation Solution
A process involving the formation of a compressively stressed silicon-based dielectric layer by depositing a thin silicon layer over an inter-layer dielectric, allowing oxygen and nitrogen to diffuse and react, resulting in a high-density etch stop layer with enhanced etch resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional etch stop layer is used, then the manufacturing process is simple, but over-etching occurs leading to device defects
Solution Approach 1:
The patent employs a composite etch stop layer structure consisting of a first etch stop layer (silicon nitride) and a second etch stop layer (silicon oxide) with distinct etch selectivities. This composite structure provides superior etch resistance and prevents over-etching while maintaining manufacturability through standard deposition processes.
Solution Approach 2:
The patent applies different materials with different etch resistances at different locations in the stack. The first etch stop layer (silicon nitride) provides high etch resistance to the first etch process, while the second etch stop layer (silicon oxide) provides etch resistance to the second etch process, optimizing local protection where needed.
2Manufacturing precision
If mask alignment precision is improved, then via formation accuracy increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent forms etch stop layers with specific selectivities before the via etching processes. These pre-formed layers act as protective barriers that prevent over-etching and compensate for minor mask alignment variations, reducing the stringency of alignment requirements while maintaining via formation precision.
Solution Approach 2:
The etch stop layers serve as cushioning layers that absorb excess etching beyond the intended via depth. This beforehand protection prevents damage to underlying structures even when etching conditions vary or alignment is slightly off, ensuring precise via formation without requiring extreme process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high-density etch stop layer significantly increases etch resistance, preventing over-etching and improving the manufacturing process for integrated circuits by ensuring precise formation of vias and contacts.
Implementation Method 1
allowing oxygen and or nitrogen to diffuse into and react within the thin silicon layer to transform the thin silicon layer into a silicon-based dielectric layer
Implementation Method 2
allowing oxygen and or nitrogen to diffuse into and react within the thin silicon layer to transform the thin silicon layer into a silicon-based dielectric layer
Implementation Method 3
the dielectric forms as a compressively stressed layer with a higher than normal density
Data Source
AI summary
Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an inter-level dielectric layer arranged over the semiconductor substrate. An etch-stop layer is arranged over the inter-level dielectric layer. The etch-stop layer comprises silicon oxide, silicon nitride, or silicon oxynitride, and has a density greater than or equal to 2.15 g/cm3.