High Density Interconnect Substrate for Microelectronic Packages
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Solution Overview
Problem
As microelectronic packages become smaller, the available space for routing traces for input/output interconnections decreases, leading to longer paths that increase resistance and reduce performance.
Innovation Solution
The implementation of a high-density interconnection method using an interconnect substrate with electrically isolated conductive traces aligned in the x-direction, connecting microelectronic device connection structures to form efficient and redundant pathways between microelectronic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If microelectronic packages are made smaller to reduce device size, then the package footprint is reduced, but the available space for routing traces decreases leading to longer paths and increased resistance
Solution Approach 1:
The patent transitions from planar trace routing to three-dimensional vertical interconnection using through-substrate vias and stacked layers. This allows signals to travel vertically through the substrate rather than along the surface, effectively adding a Z-dimension to the interconnection path and enabling shorter routes despite reduced package footprint.
Solution Approach 2:
The patent implements multiple interconnection layers nested within the substrate thickness, with conductive traces and vias arranged in stacked configurations. This nesting approach allows multiple signal paths to be embedded within the substrate volume, increasing interconnect density without increasing the package footprint.
2Area of stationary object
If trace paths are extended to accommodate smaller package sizes, then the package footprint is reduced, but resistance increases due to longer conduction paths
Solution Approach 1:
The patent uses vertical through-substrate vias to create three-dimensional interconnection paths, allowing signals to travel perpendicular to the substrate surface rather than along extended planar paths. This dimensional change dramatically shortens the conduction distance and reduces resistance while maintaining a compact footprint.
Solution Approach 2:
The patent combines multiple short vertical via segments with horizontal trace segments in a stacked configuration, creating a series of short interconnection steps rather than one long continuous path. This segmentation and recombination approach minimizes the total trace length and reduces cumulative resistance.
3Reliability
If interconnect density is increased to improve performance, then resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the interconnection structure into discrete modular layers with through-substrate vias and separate trace levels. This segmentation allows each layer to be manufactured and aligned independently, reducing the cumulative precision requirements compared to a single complex planar routing layer.
Solution Approach 2:
The patent uses the substrate itself as an intermediary structure that provides mechanical support and alignment references for the conductive traces and vias. The substrate's rigid structure and defined geometry serve as a precise template for positioning interconnect elements, reducing the need for ultra-precise direct alignment between distant features.
Data Source
AI summary
A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.