High Density Memory Modules Using Stacked PCBs
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Solution Overview
Problem
Conventional memory modules have limitations in terms of size and interconnect efficiency, which restricts their density and flexibility in modern computing systems, particularly when interfacing with devices like FPGAs, microprocessors, and ASICs.
Innovation Solution
The development of high-density semiconductor memory modules utilizing 3D packaging technologies, such as stacked printed circuit boards with direct pin-outs for improved interconnectivity, reduced footprint, and enhanced signal integrity, along with the use of solid state memory devices and advanced interconnect solutions like void-free overmold and high-density surface mount technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory modules are used with standardized pin assignments, then compatibility with system buses is improved, but memory density and module size are limited
Solution Approach 1:
The patent transitions from conventional 2D memory module layouts to a 3D stacked architecture where multiple PCB boards are vertically stacked. Memory devices are mounted on multiple layers of PCBs connected through vertical interconnects, enabling increased memory density without proportionally increasing the module footprint. This dimensional transition allows the module to utilize vertical space efficiently, achieving higher capacity in a compact form factor.
2Speed
If memory modules use standardized carrier connectors, then ease of installation is improved, but interconnect efficiency and operating speed are reduced
Solution Approach 1:
The memory module is segmented into multiple functional PCB boards stacked vertically, with each board containing specific memory devices or interconnect structures. This segmentation allows optimized signal paths within each layer while maintaining overall module functionality. The divided architecture enables shorter trace lengths and reduced signal degradation compared to conventional single-board designs, improving operating speed despite increased structural complexity.
Solution Approach 2:
The patent introduces intermediary structures such as voltage reference generators, termination resistors, and buffer circuits integrated on the PCB boards to enhance signal integrity and interoperability. These intermediary components act as mediators between the memory devices and the host system, ensuring reliable data transmission at higher speeds while managing the complexity of the stacked interconnect architecture.
3Reliability
If multiple memory chips are mounted on a single PCB, then manufacturing simplicity is improved, but signal integrity and thermal management deteriorate
Solution Approach 1:
By stacking multiple PCB boards vertically, the patent distributes memory devices across three-dimensional space rather than concentrating them on a single plane. This spatial distribution reduces signal interference and thermal density on any individual board, improving signal integrity and heat dissipation. The vertical arrangement allows better airflow and thermal management compared to densely packed single-board configurations.
4Quantity of substance
If memory modules are designed for high density, then memory capacity is improved, but power requirements and thermal challenges increase
Solution Approach 1:
The patent implements local quality optimization by placing voltage reference generators and power management circuits on specific PCB boards closest to the memory devices they serve. This localized power delivery reduces voltage drops and power consumption by minimizing current travel distance. Additionally, thermal vias and heat dissipation structures are strategically positioned in high-density regions to efficiently manage local heat generation, enabling high capacity without proportional power and thermal penalties.
Data Source
AI summary
Solid state memory modules are disclosed having increased density for module size/footprint. Different embodiments also provide for improved interconnect arrangements between the memory modules and the corresponding field programmable gate array (FPGA), micro-processor (μP), or application-specific integrated circuit (ASIC). These interconnects provide for greater module interconnect flexibility, operating speed and operating efficiency. Some memory module embodiments according to the present invention comprises a plurality of solid state memory devices arranged on a first printed circuit board. A second printed circuit board is on and electrically connected to the first printed circuit board, with the second printed circuit board having a pin-out for direct coupling to a host device.