High Density Resistance Semiconductor Device
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Solution Overview
Problem
Manufacturing high-density memory devices with metal-oxide based memory cells faces challenges in achieving tight process tolerances and multi-level operation due to variations in manufacturing processes, especially when reducing the cross-sectional area of individual memory cells.
Innovation Solution
A memory device structure comprising a diode and multiple metal-oxygen compound memory elements arranged in series along a current path between word and bit lines, with specific dimensions and separation distances to achieve high density and multi-level operation, and a method for manufacturing these devices involving the formation of word and bit lines, vias, and memory elements using dielectrics and semiconductor regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the cross-sectional area of memory cells is reduced to achieve higher density, then memory density is improved, but manufacturing precision deteriorates due to tight tolerance requirements and process variations
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a 3D vertical structure by stacking multiple memory elements (first memory element, second memory element, third memory element) in series along the vertical direction. This dimensional change allows memory density to increase without proportionally reducing the cross-sectional area, thereby maintaining manufacturability while achieving higher capacity.
Solution Approach 2:
The patent embeds multiple memory elements within a single memory cell footprint by stacking them vertically. The first, second, and third memory elements are nested along the current path between word line and bit line, effectively packing more storage capacity into the same planar area without requiring proportionally smaller feature sizes.
2Quantity of substance
If multiple memory elements are stacked vertically to achieve high density, then memory density is improved, but device complexity increases
Solution Approach 1:
The patent employs a diode structure that serves multiple functions: it provides selective access to the stacked memory elements, enables multi-level cell operation through its non-linear I-V characteristics, and facilitates read-disturb-free operation. This multi-functional component reduces the need for additional access transistors that would otherwise increase device complexity.
Solution Approach 2:
The patent combines multiple memory elements (first, second, and third memory elements) into a single series-connected stack within one memory cell. This merging approach allows the cell to store multiple bits of data (multi-level operation) while using a unified structural framework, thereby achieving high density without proportionally increasing the number of separate cell units.
3Manufacturing precision
If tight process tolerances are enforced to meet small feature size requirements, then manufacturing precision is improved, but productivity deteriorates
Solution Approach 1:
The patent changes the critical scaling parameter from lateral feature size to vertical stacking height. By moving the miniaturization focus to the vertical dimension, the design relaxes lateral tolerance requirements, allowing larger and more manufacturable lateral feature sizes while still achieving high density through increased vertical integration. This parameter shift improves productivity by reducing the stringency of lithographic constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-density memory arrays with multi-level operation by controlling the resistive states of metal-oxide based memory elements, allowing for efficient data storage and precise manufacturing processes, thereby addressing the challenges of tight tolerance requirements and small feature sizes.
Implementation Method 1
Metal oxide based nonvolatile resistive random access memory RRAM has attracted much attention because of its simple structure and excellent properties such as low power, high speed, and a large memory window between resistive states. Tungsten-oxygen WOx based RRAM can be caused to change resistance between two or more stable ranges by application of electrical pulses
Data Source
AI summary
Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Each memory cell comprises a diode and a plurality of memory elements each comprising one or more metal-oxygen compounds, the diode and the plurality of memory elements arranged in electrical series along a current path between a corresponding word line and a corresponding bit line.