High-Density Stacked Vertical SRAM Layout for Smaller Cell Area
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Solution Overview
Problem
Existing SRAM cells occupy a large area on integrated circuit chips, requiring more space and increasing power consumption, while traditional bit line connections complicate access operations.
Innovation Solution
A non-rectangular layout is employed for SRAM cells with vertically stacked transistors, including pull-up and pull-down transistors, and pass-gate transistors at opposite ends, connected by vertical gate contacts, reducing the overall cell area and simplifying bit line connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional planar SRAM cell layout is used, then transistors can be easily fabricated with standard processes, but the cell area is large occupying significant chip space
Solution Approach 1:
The patent transitions from planar 2D transistor layout to 3D vertical stacking, arranging pull-up and pull-down transistors in vertical layers above each other. This dimensional change reduces the horizontal footprint of each SRAM cell while maintaining all necessary transistor connections through vertical gate contacts and source/drain regions.
Solution Approach 2:
The patent implements nested transistor structures where pull-up transistors are positioned vertically above pull-down transistors, with shared source/drain regions serving multiple functions. The gate contacts and interconnect structures are nested within the vertical column, maximizing space utilization and reducing overall cell area.
2Quantity of substance
If more SRAM cells are packed per chip, then memory capacity increases, but power consumption increases proportionally
Solution Approach 1:
By stacking transistors vertically, the patent increases the number of cells per unit chip area without proportionally increasing total transistor count per cell. This allows higher cell density with reduced per-cell power consumption, as the vertical structure reduces parasitic capacitances and improves drive efficiency.
Solution Approach 2:
The patent modifies electrical parameters through the vertical structure, including reduced gate lengths, optimized channel widths, and adjusted doping profiles in the stacked transistors. These parameter changes improve transistor performance and reduce leakage currents, thereby lowering overall power consumption while increasing cell count.
3Ease of operation
If vertical gate contacts are used to connect stacked transistors, then bit line connections are simplified, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication techniques where gate contacts are positioned using the transistor gates themselves as alignment references. Source and drain regions are formed with precise alignment to gate structures before vertical stacking, eliminating the need for complex post-fabrication alignment and reducing precision requirements during assembly.
Solution Approach 2:
The patent introduces intermediate connection structures such as conductive plugs and vias that facilitate vertical connections between stacked transistors. These intermediary elements provide robust mechanical and electrical connections while accommodating minor alignment variations, reducing the stringency of precision requirements.
Data Source
AI summary
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a static random access memory (SRAM) cell. The SRAM cell may include a first section of the SRAM cell with a first pull-up transistor, first pull-down transistor, and first pass-gate transistor. The SRAM cell may include a second section of the SRAM cell with a second pull-up transistor, second pull-down transistor, and second pass-gate transistor. The first section of the SRAM cell and the second section of the SRAM cell may be arranged in a non-rectangular cell layout with the first pass-gate located at a first end of the non-rectangular cell layout and the second pass-gate at a second end of the non-rectangular cell layout opposite the first end.