High-Density Via Microfluidic Chips
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Solution Overview
Problem
Conventional methods are unable to manufacture microfluidic chips with high-density vias due to physical and cost limitations, particularly in silicon, where etching through thick wafers is challenging and wet processing can render devices unusable through capillary action.
Innovation Solution
A method involving a silicon device layer with a high density of vias, sealed by a more rigid glass or silicon sealing layer, where the device layer is thinned and vias are formed as a last step using a dry process to prevent fluidic wicking, allowing for high-density microfluidic features and protection from downstream wet processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard etching methods are used on thick silicon wafers (200 μm or 300 μm), then through-silicon vias can be formed, but the manufacturing difficulty increases significantly and cost rises
Solution Approach 1:
The patent applies preliminary action by thinning the silicon wafer to 50 μm or less before forming vias. This pre-processing step creates optimal conditions for via formation, allowing standard etching methods to successfully create through-silicon vias without the extreme difficulties associated with etching thick wafers. The thinning is performed using conventional techniques such as chemical mechanical polishing (CMP) or selective etching, which are well-established in semiconductor manufacturing.
2Ease of manufacture
If wet processing is performed after via formation, then standard semiconductor manufacturing processes can be completed, but capillary action wicks fluids into the microfluidic device rendering it unusable
Solution Approach 1:
The patent applies inversion by reversing the conventional sequence of operations. Instead of forming vias first and then sealing, the method seals the microfluidic device first and then forms the vias through the sealed structure. This inverted approach allows wet processing to occur before via formation, eliminating the capillary wicking problem because the vias are created after the device is already sealed and filled with fluid, so no wicking can occur.
Solution Approach 2:
The patent extracts the harmful capillary action effect by removing the interface between the via and the external environment during critical processing steps. By forming vias through a sealed device structure and then sealing the via openings, the method eliminates the capillary pathways that would otherwise wick fluids during wet processing, thereby extracting the harmful effect from the manufacturing process.
3Productivity
If high-density vias (≥100 vias/cm²) are integrated into silicon chips, then high-throughput sample preparation is enabled, but standard manufacturing options become physically impossible
Solution Approach 1:
The patent applies parameter changes by modifying the silicon wafer thickness parameter from the standard 200 μm or 300 μm to 50 μm or less. This parameter change enables the formation of high-density vias using standard etching and filling processes that cannot successfully create such dense via patterns in thicker wafers. The thinning allows for better etch uniformity, easier via breakthrough, and more effective filling processes, thereby making high-density via integration manufacturable with conventional techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the creation of microfluidic chips with hundreds to tens of thousands of vias per square centimeter, facilitating high-throughput sample preparation and protecting sealed microfluidic features from wet processing, thus overcoming the limitations of traditional manufacturing techniques.
Implementation Method 1
Wet processes can wick these fluids into the microfluidic device through capillary action, rendering the device unusable.
Data Source
AI summary
Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.