High-Drive Standard Cell Layout With Midline Power Track
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Solution Overview
Problem
Traditional high-drive-multiple standard cell libraries increase driving force by expanding transverse width and using parallel connections, resulting in significant area loss.
Innovation Solution
A layout structure with a power line track in the middle of the standard cell, first-layer metal wires at its ends, intermediate wiring through additional metal wires, ground wires at top and bottom, and PMOS and NMOS transistors positioned accordingly, optimizing area usage and driving force.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transverse width is increased and parallel connection is adopted to increase driving force, then driving force is improved, but area is greatly lost
Solution Approach 1:
The patent changes the power line track from a horizontal arrangement (traditional topmost track) to a vertical arrangement (middle track along length direction). This dimensional reorientation allows PMOS transistors to be positioned directly below the power line, enabling more efficient use of vertical space and reducing the need for horizontal expansion to achieve high driving force.
Solution Approach 2:
The standard cell is divided into distinct regions: PMOS transistors in the upper portion directly below the power line track, and NMOS transistors in the lower portion adjacent to ground wires. This segmentation allows independent optimization of each transistor type's positioning and sizing, maximizing driving force while controlling area.
2Power
If PMOS transistors are positioned as close to power line as possible with maximized size, then driving force is improved, but area consumption increases
Solution Approach 1:
The patent applies different layout strategies to different transistor types: PMOS transistors are positioned directly below the power line track with maximized width for high driving force, while NMOS transistors are positioned adjacent to ground wires. This localized optimization allows each region to be tailored for its specific function, maximizing overall cell performance within area constraints.
Data Source
AI summary
The present application provides a layout structure of a high-drive-multiple standard cell library, a power line track disposed in the middle of a standard cell along a length direction thereof, the length of the power line track being in flush with the width of the standard cell, two ends of the power line track being respectively provided with first-layer metal wires, a length direction of the first-layer metal wires being along a length direction of the standard cell, the intermediate wiring of the power line track being realized through a metal wire other than the first-layer metal wires; ground wires located at the topmost and bottommost positions of the standard cell, the ground wires being connected to the first-layer metal wires; PMOS transistors located directly below the power line track; NMOS transistors located at upper and lower ends of the standard cell and adjacent to the ground wires.