High Electron Affinity Dielectric Layer for RRAM Cycling Reliability
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Solution Overview
Problem
Resistive random-access memory (RRAM) cells are prone to becoming stuck in a low resistance state during cycling, leading to hard failure bits that overwhelm error correction code capacity and potentially cause memory array failure.
Innovation Solution
Incorporating a high electron affinity (HEA) dielectric layer closest to the bottom electrode, vertically stacked with other dielectric layers of varying material systems and compositions, reduces the likelihood of RRAM cells becoming stuck during cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single dielectric layer is used in RRAM cells, then the device structure is simple and manufacturing is easier, but the reliability deteriorates as cells become stuck in low resistance state during cycling
Solution Approach 1:
The single dielectric layer is segmented into multiple dielectric layers with different electron affinities. The patent applies segmentation by dividing the dielectric layer into at least two distinct layers: a first dielectric layer with high electron affinity (HEA) and a second dielectric layer with low electron affinity (LEA). This segmentation allows each layer to perform specialized functions - the HEA layer prevents electron accumulation that causes sticking, while the LEA layer maintains the necessary resistance characteristics for memory operation.
Solution Approach 2:
Different regions of the dielectric structure are assigned different material properties (electron affinity) to serve different functions. The patent applies local quality by positioning the HEA dielectric layer specifically at the bottom electrode interface where electron accumulation occurs, while the LEA dielectric layer is positioned in the upper region. This spatial differentiation of material properties allows the structure to simultaneously prevent sticking and maintain operational resistance.
2Reliability
If multiple dielectric layers with different electron affinities are used, then the likelihood of cells becoming stuck is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the electron affinity parameter across different dielectric layers. The first dielectric layer is selected with high electron affinity (e.g., Al2O3, SiO2, HfO2, TiO2, Ta2O5, ZrO2, WO3, Nb2O5, MoO3, ZnO, In2O3, Ga2O3, AlN, SiN, Si3N4, B2O3, HfN, TiN, TaN, ZnS, In2S3, Ga2S3) while the second dielectric layer is selected with low electron affinity. This parameter differentiation is achieved through controlled material selection and deposition processes, enabling the patent to reduce hard failure bits while managing manufacturing complexity through established thin-film deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces the occurrence of hard failure bits, conserves error correction code capacity, and minimizes the risk of memory array failure without the need for additional integrated circuit area.
Implementation Method 1
the first dielectric layer is closest to the bottom electrode and has a highest electron affinity amongst the dielectric layers
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.