High-Frequency Device Integrated Attenuator and Impedance Matching
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Solution Overview
Problem
Existing high-frequency devices require separate components for attenuators and impedance matching circuits, leading to variations in characteristics and increased manufacturing time, and they are not optimized for compact size, particularly in applications like cellular phones.
Innovation Solution
A high-frequency device is designed as a single chip with stacked dielectric and magnetic layers, incorporating pattern conductors and via conductors to form signal lines with specific resistances and impedances, allowing for integrated attenuator and impedance matching functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If discrete circuit devices are used for attenuator and impedance matching circuit, then manufacturing flexibility is maintained, but manufacturing time increases and size increases
Solution Approach 1:
The patent combines the attenuator and impedance matching circuit into a single integrated chip structure. The signal line includes both the attenuator portion (with magnetic layers for attenuation) and the impedance matching circuit (with capacitors and inductors) formed on the same substrate, eliminating the need for separate discrete components and reducing assembly time.
Solution Approach 2:
The patent transitions from a planar arrangement of discrete components to a three-dimensional stacked structure with multiple layers (dielectric layers and magnetic layers). This vertical integration allows multiple circuit functions to be packed into a compact volume, reducing both manufacturing time and overall device size.
2Volume of moving object
If discrete circuit devices are used for attenuator and impedance matching circuit, then component replacement is easier, but circuit size increases
Solution Approach 1:
The attenuator and impedance matching circuit are merged into a single chip with multiple functional layers. The signal line integrates resistive portions (from magnetic layers), capacitive portions (from dielectric layers with electrodes), and inductive portions, all within one compact structure, dramatically reducing overall circuit volume.
Solution Approach 2:
The patent employs a nested multi-layer structure where dielectric layers and magnetic layers are stacked alternately. Each layer contains conductive patterns that form different circuit elements, with via holes connecting adjacent layers. This nesting allows multiple circuit functions to coexist in a compact vertical arrangement.
3Reliability
If separate attenuator and impedance matching circuit are used, then design flexibility is maintained, but characteristic variations increase
Solution Approach 1:
By integrating the attenuator and impedance matching circuit on the same chip with controlled interconnections, the patent ensures consistent electrical characteristics. The signal line provides a direct, controlled impedance path between the attenuator's input/output terminals and the impedance matching circuit, eliminating variability introduced by discrete component connections.
Solution Approach 2:
The patent controls key parameters such as the resistance of the attenuator (through magnetic layer properties), capacitance (through dielectric layer and electrode configuration), and inductance (through conductor trace geometry) to achieve desired attenuation and impedance matching characteristics with minimal variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables suppression of undesired reflections and adjustment of attenuation and impedance in a compact form, reducing variations and size, while simplifying manufacturing by integrating attenuator and impedance matching circuits in a single chip.
Implementation Method 1
a first portion of the signal line includes at least one of a via conductor extending through one magnetic layer and a pattern conductor sandwiched between two magnetic layers, and the first portion has a predetermined resistance to the high-frequency signal
Implementation Method 2
a second portion of the signal line includes at least one of a capacitor formed of two pattern electrodes in such a manner that at least one dielectric layer is sandwiched therebetween
Data Source
AI summary
A high-frequency device includes a substrate including a plurality of layers that are stacked on top of one another and that include dielectric and magnetic layers, terminals, pattern conductors each formed on one layer, and via conductors each extending through one layer. The pattern conductors and via conductors connect the terminals and form a signal line that transmits a high-frequency signal. A first portion of the signal line includes a via conductor extending through one magnetic layer and/or a pattern conductor sandwiched between two magnetic layers and has a predetermined resistance to the high-frequency signal. A second portion of the signal line includes a capacitor formed of two pattern electrodes with at least one dielectric layer and no magnetic layers sandwiched there between and/or an inductor including a pattern conductor formed on a dielectric layer. The high-frequency device has an impedance to the high-frequency signal at the terminals.