High Frequency Switch Bridge Topology for Low Loss Power Handling

The patent divides the switching function into multiple transistors (Q1-Q4) arranged in a bridge configuration, where each transistor handles a portion of the power signal. This segmentation allows the system to achieve high power handling capability through combined operation while maintaining low passing loss by ensuring that individual transistors operate in their optimal performance range rather than requiring excessive gate width in a single device.

The patent introduces capacitors (C1-C4) as intermediary elements connected to the gate terminals of the transistors. These capacitors serve as mediators that isolate the high-frequency power signal from the gate control signals, enabling the transistors to maintain excellent shutoff properties while handling high power levels. The capacitors prevent high-frequency signal leakage into the gate control circuitry, thereby maintaining low passing loss even with enhanced power handling capability.

The patent segments the power handling function across multiple transistors (Q1-Q4) in a bridge configuration, allowing each transistor to operate with moderate gate width while collectively achieving high power handling capability. This segmentation prevents any single transistor from requiring excessive gate width that would compromise shutoff properties.

Capacitors (C1-C4) are introduced as intermediary elements between the high-frequency power signal paths and the gate control terminals. These capacitors block high-frequency signal leakage into the gate control circuitry, ensuring that transistors maintain excellent shutoff properties even when operating at enhanced power levels. The capacitors effectively isolate the power signal from the control signals.