High Gain Transistor Structure Without LDD Regions
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Solution Overview
Problem
As CMOS technology advances into the nano-regime, the gain of CMOS transistors decreases, affecting their effectiveness in analog applications.
Innovation Solution
The formation of high gain transistors without lightly doped drain (LDD) regions or halo regions, where heavily doped regions serve as source/drain regions, aligned with the outer edges of sidewall spacers on the gates, enhancing the transconductance and output resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS transistor structures with LDD regions and halo doping are used, then manufacturing process compatibility is maintained, but transistor gain decreases in the nano-regime
Solution Approach 1:
The patent removes the LDD region and halo doping from the transistor structure, extracting the problematic components that were causing gain degradation. This leaves only the essential source/drain regions directly adjacent to the gate, simplifying the structure while improving performance in the nano-regime
Solution Approach 2:
The patent changes the doping parameter distribution by eliminating the gradual doping profile of LDD regions and the concentrated halo doping, replacing them with uniformly heavily doped source/drain regions. This parameter change optimizes the electric field distribution and improves transistor gain
2Reliability
If LDD regions and halo doping are used, then short-channel effects are suppressed, but channel length modulation and drain-induced barrier lowering increase
Solution Approach 1:
The patent converts the harmful effects of LDD and halo doping into benefits by their complete removal. The absence of these regions eliminates the mechanisms that cause channel length modulation and drain-induced barrier lowering, while the heavily doped source/drain regions directly adjacent to the gate provide the necessary field effect to suppress short-channel effects
3Reliability
If heavily doped source/drain regions are placed directly adjacent to the gate, then transconductance increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs sidewall spacers as preliminary structures that define the precise location of the heavily doped source/drain regions. The spacers are formed first, and then doping is performed adjacent to them, ensuring accurate alignment without requiring direct lithographic alignment of the source/drain regions to the gate
Data Source
AI summary
A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions.


