High-Ge SiGe Source-Drain Structure for Low-Resistance FinFET Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional fabrication processes face challenges in scaling integrated circuits to the 10 nanometer node or sub-10 nanometer node range due to variability, limiting the integration of new technologies and methodologies required for future technology nodes.
Innovation Solution
The introduction of silicon germanium (SiGe) channel structures with high germanium content in source and drain regions, combined with a capping layer, to provide strain and reduce contact resistance, utilizing epitaxial growth and low-temperature chemical vapor deposition for conformal metal-semiconductor junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or smaller
Solution Approach 1:
The patent changes material composition parameters by incorporating silicon germanium (SiGe) with varying germanium concentrations in source and drain regions. This material parameter change enables precise control of strain and electrical properties at 10nm node, achieving manufacturing precision requirements that conventional silicon-based processes cannot meet
Solution Approach 2:
The patent employs composite materials consisting of silicon germanium (SiGe) channel structures with high germanium content combined with capping layers. This composite approach creates a multi-layered structure that simultaneously provides strain engineering benefits and contact resistance reduction, resolving the precision-complexity contradiction through advanced material composition
2Reliability
If high germanium content is used in source and drain regions, then transistor performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the SiGe channel structure with high germanium content in source and drain regions before final device assembly. This advance preparation of the strained semiconductor structure ensures optimal transistor performance is established early in the fabrication process, accommodating subsequent manufacturing steps
Solution Approach 2:
The patent utilizes parameter changes by controlling germanium concentration in the SiGe material and adjusting epitaxial growth conditions. These parameter optimizations enable high transistor performance through enhanced strain effects while managing fabrication complexity through controlled material deposition processes
3Manufacturing precision
If epitaxial growth and low-temperature CVD are used, then manufacturing precision is improved, but use of energy increases
Solution Approach 1:
The patent employs phase transitions in the chemical vapor deposition process, utilizing low-temperature conditions to control the deposition phase and achieve conformal metal-semiconductor junctions. This phase transition approach enables precise conformal coating while managing thermal energy input through controlled chemical reactions rather than high-temperature thermal processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by improving strain and reducing contact resistance, enabling efficient fabrication of advanced integrated circuits with improved drive current and reduced resistance.
Implementation Method 1
silicon germanium (SiGe) channel structures with high germanium content in source and drain regions, combined with a capping layer, to provide strain
Implementation Method 2
utilizing epitaxial growth and low-temperature chemical vapor deposition for conformal metal-semiconductor junctions
Implementation Method 3
utilizing epitaxial growth and low-temperature chemical vapor deposition for conformal metal-semiconductor junctions
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a relatively high germanium content are described. In an example, an integrated circuit structure includes a fin including a semiconductor material. A gate stack is over an upper fin portion of the fin. A first epitaxial source or drain structure is embedded in the fin at a first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at a second side of the gate stack. The first and second epitaxial source or drain structures include silicon and germanium and have a same or greater atomic concentration of germanium than the fin.