High-Impedance Load Circuit Using Switched Capacitive Biasing
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Solution Overview
Problem
Existing electronic circuits face challenges in creating high-impedance loads for sensor applications, such as pyro-ceramic and thermopile sensors, due to issues like process parameter and temperature dependence, large silicon area requirements, and cost implications, while maintaining predictable operation and minimizing signal degradation.
Innovation Solution
An electronic circuit configuration using a capacitive element and non-linear voltage-to-current relationship elements, with switching elements and timing control logic to establish a high-impedance load through charging, discharging, and transfer stages, allowing for the creation of high-impedance terminating elements without excessive silicon usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If low-doped sheet resistors are used to create high resistive elements, then the resistive impedance is improved, but the silicon area increases and parasitic capacitances degrade sensor signals
Solution Approach 1:
The patent changes the operating parameters of MOSFET devices by biasing them in the subthreshold region, where the drain current follows an exponential relationship with gate-source voltage. This allows the circuit to achieve extremely high effective impedance (greater than 10^12 ohms) without requiring large physical resistor areas, as the impedance is controlled by voltage biasing rather than physical dimensions
Solution Approach 2:
The patent replaces passive resistive elements with active MOSFET devices operating in subthreshold mode. Instead of using physical resistor geometry to achieve high impedance, the invention uses the exponential current-voltage characteristics of MOSFETs in weak inversion, substituting a voltage-controlled active mechanism for a geometry-dependent passive component
2Manufacturing precision
If large area resistors are used to achieve high resistance, then the resistive load is improved, but the parasitic capacitance increases and degrades small sensor signals
Solution Approach 1:
The patent changes the operating state of MOSFET devices to subthreshold bias conditions, where the exponential relationship between gate-source voltage and drain current creates an extremely high dynamic output impedance. This parameter change allows achieving high resistive load characteristics without the large physical areas that would otherwise be required, thereby minimizing parasitic capacitance
Solution Approach 2:
The patent employs dynamic biasing of MOSFET devices in the subthreshold region, where small changes in gate voltage produce exponential changes in drain current. This dynamic operation allows the circuit to maintain high effective impedance while using minimal silicon area, avoiding the static large-area resistors that would create harmful parasitic capacitance
3Area of stationary object
If subthreshold MOSFET characteristics are used to achieve high impedance, then the silicon area is reduced, but the biasing complexity increases
Solution Approach 1:
The patent segments the biasing function into separate controllable stages using switching elements. The bias voltage is applied in discrete time intervals rather than continuously, allowing independent control of each MOSFET's operating state. This segmentation simplifies the overall biasing complexity by breaking down the continuous control problem into manageable discrete steps
Solution Approach 2:
The patent employs periodic application of bias voltages to MOSFET devices through switching elements controlled by timing signals. By applying subthreshold bias conditions in periodic pulses rather than continuously, the circuit achieves the required high impedance states while using simple switching control logic, reducing the overall biasing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively presents a high-impedance load that is robust, cost-effective, and maintains signal integrity by using subthreshold MOSFET characteristics and diode or BJT exponential relationships, addressing the limitations of prior solutions and ensuring reliable operation across temperature ranges.
Implementation Method 1
a capacitive element (C) provided between a first node (Node A) and the reference point
Implementation Method 2
utilise the exponential current-voltage relationship of a diode or BJT (Bipolar Junction Transistor), to enable the implementation of circuit elements that behave as extremely high-impedance devices
Implementation Method 3
use subthreshold characteristics of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, or to utilise the exponential current-voltage relationship of a diode or BJT (Bipolar Junction Transistor), to enable the implementation of circuit elements that behave as extremely high-impedance devices
Data Source
AI summary
An electronic circuit configured to present a high-impedance load between a load point and a reference point includes a capacitive element (C) provided between a first node (Node A) and the reference point, a first element (D1) connected in parallel with the capacitive element (C), a first switching element (S1) provided in series between the first node (A) and a voltage source point, a second switching element (S2) provided between the first node (A) and a second node (Node B), a second element (D2) connected between the second switching element (S2), the load point, and the reference point, and timing control logic configured to implement three stages. In a charging stage, the first switching element (S1) is closed and the second switching element (S2) to charge a nodal voltage vD(t) at the first node (A). In discharge stage, the first switching element (S1) is open and the second switching element (S2) is open to enable discharging of the capacitive element (C) through the first element (D1). In a transfer stage, the second switching element (S2) is closed to connect the first node (A) and the second node (B), after which the second switching element (S2) is opened and the second element (D2) is biased to present the high-impedance load.