High Impedance Memory Test Architecture for Signal Integrity
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Solution Overview
Problem
High-speed electronic device testing using automated test equipment faces challenges in maintaining signal integrity and temperature range due to long transmission lines and power constraints, especially for memory devices that cannot source enough current to drive 50 ohm termination resistors, limiting data rate and altering electrical characteristics.
Innovation Solution
The use of semiconductor devices fabricated using metal-on-insulator or silicon-on-insulator technology to create driver/receiver pairs that can be mounted directly to the probe head, reducing the need for long transmission lines and enabling low leakage currents across a wide temperature range, allowing for optimized data rates and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If long transmission lines are used to connect the driver/receiver to the device under test, then the testing can be performed with standard probe head distances, but signal integrity deteriorates and reflections occur requiring 50 ohm termination resistors
Solution Approach 1:
The patent introduces an intermediary solution by placing driver/receiver semiconductor devices directly on the probe head, which act as intermediate components between the test equipment and the device under test. This eliminates the need for long transmission lines while maintaining signal integrity, as the driver/receiver are positioned at the optimal location rather than requiring long-distance signal transmission through cables.
2Reliability
If 50 ohm termination resistors are used to prevent reflections on long transmission lines, then signal reflections are reduced, but the device under test cannot source enough current and data rate is limited to approximately 10 MHz
Solution Approach 1:
The patent extracts the termination function from the traditional 50 ohm resistor approach and relocates it to integrated driver/receiver semiconductor devices on the probe head. This extraction allows the system to achieve proper signal termination without the current limitations of high-value termination resistors, enabling higher data rates while maintaining signal integrity.
3Reliability
If the device under test sources high current to drive 50 ohm termination resistors, then signal integrity is maintained, but power consumption increases and electrical characteristics are altered
Solution Approach 1:
The patent changes the electrical parameters of the termination system by using low-impedance driver/receiver circuits with integrated termination capabilities rather than high-impedance 50 ohm resistors. This parameter change allows proper signal termination with much lower current requirements, reducing power consumption while maintaining signal integrity and preserving the device under test's electrical characteristics.
4Device complexity
If driver/receiver are placed far from the device under test in standard ATE configuration, then the test system architecture is simplified, but transmission line effects and temperature range limitations occur
Solution Approach 1:
The patent merges the driver/receiver functions with the probe head structure by directly mounting semiconductor devices on the probe head. This consolidation eliminates the need for separate distant driver/receiver units and long transmission lines, while also enabling the system to operate across wide temperature ranges by placing the sensitive electronics close to the device under test where temperature control is more effective.
Data Source
AI summary
An electronic device for use with a probe head in automated test equipment includes first and second pluralities of semiconductor devices. The first plurality of semiconductor devices is arranged to form at least one driver arranged to couple to a device under test. The at least one driver is configured to transmit a signal to the at least one device under test. The second plurality of semiconductor devices is arranged to form at least one receiver arranged to couple to the device under test. The at least one receiver is configured to receive a signal from the at least one device under test. Each of the second plurality of semiconductor devices has a thickness less than about 300 μm exclusive of any electrical interconnects. The at least one receiver is adapted to mount directly to the probe head.