High Impedance Node Identification in Circuit Design
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Solution Overview
Problem
Current methods for identifying high-impedance nodes in circuit designs are time-consuming and inefficient, particularly due to their serial nature and incorrect identification of non-problematic nodes, which can lead to excessive power dissipation and thermal issues in mobile devices.
Innovation Solution
A method involving the addition of noise sources represented by Norton equivalent circuits to nodes of interest, computing voltage values in parallel, and designating nodes with voltage values within a predetermined range as high-impedance nodes, allowing for simultaneous identification of both hazardous and benign high-impedance nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional method of calculating equivalent resistance is used to identify high-impedance nodes, then identification accuracy is achieved, but time consumption increases significantly due to serial processing
Solution Approach 1:
The patent segments the node identification process into two distinct phases: first, a serial analysis phase that calculates equivalent resistance for each node individually to identify candidate high-impedance nodes; second, a parallel verification phase that simultaneously computes voltage values for all candidate nodes using noise sources. This segmentation allows the computationally intensive serial analysis to be followed by efficient parallel verification, resolving the time-accuracy contradiction.
Solution Approach 2:
The patent applies preliminary action by first identifying candidate high-impedance nodes through serial equivalent resistance calculation before performing the parallel voltage computation. This preliminary filtering reduces the number of nodes that require full parallel analysis, combining the benefits of thorough initial screening with efficient parallel processing of reduced candidate set.
2Ease of operation
If conventional method assumes node is Hi-Z node, then identification process is simplified, but incorrect identification of non-problematic nodes occurs
Solution Approach 1:
The patent implements feedback by using the voltage computation results as verification feedback for the initial high-impedance node identification. Nodes that were identified as high-impedance through equivalent resistance calculation are then verified by checking if their voltage values fall within the expected range when noise sources are applied. This feedback mechanism corrects incorrect identifications while maintaining operational simplicity.
Solution Approach 2:
The patent introduces noise sources as an intermediary element to bridge the gap between simple identification and accurate verification. The noise sources provide a controlled stimulus that allows measurement of actual node behavior without requiring complex analysis, serving as a mediator that transforms simple identification results into accurate verification.
3Loss of energy
If power gating approach is used to reduce static power dissipation, then power management is improved, but high impedance nodes cause excessive current paths and power dissipation
Solution Approach 1:
The patent applies preliminary action by identifying high-impedance nodes before finalizing the power gating design. By using noise sources to verify actual node behavior in advance, the design can proactively address problematic nodes through bus keepers or retention registers before they cause excessive current paths during operation, thus preventing rather than correcting power dissipation issues.
Solution Approach 2:
The patent uses feedback from noise source voltage measurements to identify nodes that require additional protection. The voltage values computed during parallel processing provide feedback about actual node impedance states, enabling the design to selectively add bus keepers or retention registers only where needed, rather than applying power gating uniformly across all nodes.
Data Source
AI summary
Various aspects of the disclosed techniques relate to techniques for identifying high-impedance nodes in a circuit design. Noise sources are added to nodes of interest in the circuit design. Voltage values at the nodes of interest are then computed in parallel. Based on the voltage values, high impedance nodes in the nodes of interest are identified.