High I/O Semiconductor Chip Package with Through Electrodes
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Solution Overview
Problem
Conventional semiconductor packages face inefficiencies in data processing speed and power consumption due to the need for long wires between memory and processor chips, which increases data writing/reading time and requires significant system space, especially when using CPUs as processors.
Innovation Solution
A high I/O semiconductor chip package is designed with through electrodes in a scribe region connecting memory and processor chips directly, reducing wire length and enabling faster data processing by arranging memory devices in an m×n matrix on a substrate and stacking a processor chip of similar size, with through electrodes connecting them to the substrate's circuit patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is read from or written to the memory device by passing through wires on a system board, then the memory device can be connected to the processor, but the data writing/reading time increases and processing time decreases
Solution Approach 1:
The patent transitions from a planar two-dimensional connection (wires on system board) to a three-dimensional stacked configuration where memory devices and processors are vertically connected through through-electrodes. This dimensional change dramatically reduces the physical distance data must travel, thereby reducing data writing/reading time and improving processing speed.
Solution Approach 2:
The patent implements a stacked package structure where memory devices are positioned above or below the processor chip, with through-electrodes penetrating through the processor chip to establish vertical connections. This nested arrangement allows memory and processor to be closely integrated in three-dimensional space, minimizing wire length and connection time.
2Area of stationary object
If a large system space is required for memory device and processor, then the components can be properly housed, but the design rules and wire length increase
Solution Approach 1:
By stacking memory devices and processors vertically in the Z-dimension rather than placing them side-by-side in the X-Y plane, the patent reduces the horizontal wire length required for connections while maintaining adequate system space for heat dissipation and manufacturing access.
Solution Approach 2:
The patent divides the system into separate functional layers (processor layer and memory layer) connected through through-electrodes, allowing each component to be optimized independently while reducing overall wire length through the vertical interconnection architecture.
3Reliability
If the length of wires is increased to connect memory and processor, then the components can be positioned for proper connection, but the power consumption increases
Solution Approach 1:
The vertical stacking architecture reduces wire length by eliminating long horizontal traces on the system board, thereby reducing the energy required to maintain data integrity over the connection path while preserving signal quality through controlled impedance design of the through-electrodes.
4Productivity
If through electrodes are arranged in a scribe region, then data transmission bandwidth and processing speed are enhanced, but the manufacturing complexity increases
Solution Approach 1:
The through-electrodes are formed in the scribe region during the wafer fabrication process before the chips are separated and packaged. This preliminary formation of interconnection structures enables subsequent stacking and bonding operations to be performed more easily, reducing overall manufacturing complexity despite the advanced architecture.
Data Source
AI summary
Provided are a high I/O semiconductor chip package in which a processor and a memory device are connected to each other via through electrodes and a method of manufacturing the high I/O semiconductor chip package. The high I/O semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, each memory device being arranged in a matrix in chip regions partitioned by a scribe region; a second semiconductor chip stacked on the first semiconductor chip; and a plurality of through electrodes arranged along peripheral portions of the memory devices and connecting the first and second semiconductor chips to the second circuit patterns of the substrate.