High Isolation Integrated Inductor with Symmetric Open-Loop Coils
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Solution Overview
Problem
The coexistence of multiple inductors on a single integrated circuit chip often results in undesired magnetic coupling, which can be mitigated only by increasing the physical separation between them, leading to larger chip sizes and higher costs.
Innovation Solution
The design incorporates a first and second coil of metal trace in an open loop topology in one metal layer and a third coil in a closed loop topology in another layer, with the first and second coils being symmetrical and a mirror image of each other, respectively, and housed by a dielectric slab on a silicon substrate, to minimize magnetic coupling through a mode selection function that suppresses odd-mode signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple inductors are placed on a single chip, then integration density is improved, but magnetic coupling between inductors increases
Solution Approach 1:
The patent employs symmetry and mirror image configurations of the first and second coils to convert the harmful magnetic coupling effect into a beneficial cancellation effect. By positioning the coils symmetrically and using mirror image topology, the magnetic fields from adjacent inductors cancel each other out, transforming the harmful coupling into a self-neutralizing system that enables higher integration density without sacrificing isolation performance.
Solution Approach 2:
The patent introduces asymmetry through the third coil's closed loop topology that encloses the first and second coils, creating an asymmetric three-dimensional structure. This asymmetric configuration, combined with the symmetric planar layout of the first two coils, generates magnetic field patterns that inherently reduce coupling with external inductors while maintaining strong internal coupling for signal transmission.
2Object-affected harmful factors
If physical separation between inductors is increased, then magnetic coupling is reduced, but chip area increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional structure by placing the third coil in a different metal layer that encloses the first and second coils vertically. This dimensional change allows the inductors to achieve magnetic isolation without increasing lateral separation, as the enclosing third coil creates a magnetic shield that confines flux lines within the vertical stack, reducing coupling with adjacent inductors on the same chip area.
3Object-affected harmful factors
If physical separation between inductors is increased, then magnetic coupling is reduced, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple inductor functions into a single integrated structure where the first, second, and third coils form a unified inductor unit. This merged configuration achieves magnetic isolation through the symmetric mirror image topology and enclosing structure, eliminating the need for large physical separations between independent inductors. The result is a compact design that reduces chip area and manufacturing cost while maintaining effective magnetic coupling suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively isolates the inductor from other inductances on the chip by suppressing unwanted magnetic coupling, allowing for a smaller chip area and reduced costs while maintaining even-mode signal integrity.
Implementation Method 1
there might exist an undesired magnetic coupling among said multiple inductors
Implementation Method 2
minimize magnetic coupling through a mode selection function that suppresses odd-mode signals
Data Source
AI summary
An inductor having a first coil of metal trace configured in an open loop topology and placed in a first metal layer; a second coil of metal trace configured in an open loop topology and placed in the first metal layer; and a third coil of metal trace configured in a closed loop topology and placed in a second metal layer, wherein: the first coil of metal trace is laid out to be substantially symmetrical with respect to a first axis, the second coil of metal trace is laid out to be approximately a mirror image of the first coil of metal trace with respect to a second axis, and the third coil of metal trace is laid out to enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective.

