High-K Blocking Dielectric for Deeper Erase in Charge-Trap Memory
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Solution Overview
Problem
Conventional non-volatile semiconductor memories face limitations in program and erase window due to the saturation of erase mode threshold voltage, restricting the performance of SONOS transistors.
Innovation Solution
Incorporation of a high dielectric constant blocking region, either as a bi-layer or graded dielectric layer, in the gate stack of non-volatile charge trap memory devices to mitigate electron back-streaming and enhance the program and erase window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional blocking layer is used in the gate stack, then the device structure is simple and easy to manufacture, but the erase mode threshold voltage saturates with time, limiting the program and erase window
Solution Approach 1:
The blocking layer is segmented into multiple dielectric layers with different dielectric constants. The patent introduces a first dielectric layer with a first dielectric constant and a second dielectric layer with a second dielectric constant greater than the first, positioned adjacent to the charge trapping layer. This segmentation allows each layer to perform different functions: the first layer provides basic blocking while the second high-k layer enhances the program and erase window by reducing electron back-streaming, thereby resolving the contradiction between simple structure and improved reliability.
Solution Approach 2:
The patent employs composite dielectric materials with different dielectric constants in the blocking layer region. By combining a conventional dielectric material (first dielectric layer) with a high-k dielectric material (second dielectric layer), the structure achieves both the electrical blocking function and the enhanced charge trapping capability needed for improved program and erase window, while maintaining manufacturability through standard deposition processes.
2Reliability
If the blocking layer thickness is increased to reduce electron back-streaming, then the program and erase window improves, but the device area and complexity increase
Solution Approach 1:
The patent changes the dielectric constant parameter of the blocking layer by introducing a high-k dielectric material in the second dielectric layer. This parameter change allows achieving the same electron back-streaming reduction effect with a thinner overall blocking structure compared to using only conventional dielectric materials, thereby improving erase depth without proportionally increasing device area.
Solution Approach 2:
By using composite dielectric layers with different dielectric constants, the patent achieves enhanced electron blocking capability in a compact structure. The high-k second dielectric layer provides superior electrical properties that allow for reduced physical thickness while maintaining or improving the program and erase window, thus resolving the area versus reliability contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high dielectric constant blocking region allows for a deeper erase and greater differential between erase and program modes, improving the performance and scalability of non-volatile charge trap memory devices.
Implementation Method 1
a high dielectric constant blocking region... to mitigate electron back-streaming
Data Source
AI summary
An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.