High-k Dielectric Uniformity in VT FinFETs via Protective Apron
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Solution Overview
Problem
The challenge lies in forming high-k dielectric device features with dimension uniformity, particularly in recessed high-k dielectric layers, to control feature uniformity and prevent under-etching relative to neighboring non-high-k device features, especially in vertical transport fin field effect transistors (VT FinFETs).
Innovation Solution
A method involving the formation of a multilayer fin structure with specific trim layers and recess fillers, followed by the deposition of a high-k dielectric layer, which is then trimmed to ensure uniformity and positioning, using a protective apron and overhanging fin template to shield the high-k dielectric layer during etching, thereby controlling the terminal ends of the high-k dielectric layer and maintaining dimensional uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional FET structures are used, then device fabrication is simpler, but device dimensions cannot be scaled down effectively
Solution Approach 1:
The gate structure is segmented into multiple functional layers: high-k dielectric layer for electrical isolation, protective apron for dimensional control, and overhanging fin template for etch shielding. This segmentation allows each layer to perform its specific function independently, enabling precise control of gate length and width while maintaining fabrication feasibility
Solution Approach 2:
The protective apron and overhanging fin template are formed beforehand to establish precise dimensional boundaries before the final etching step. The protective apron is deposited and patterned to define the gate length, while the overhanging fin template is formed to extend beyond the gate structure, providing preliminary shielding against under-etching before the actual gate etch occurs
2Manufacturing precision
If high-k dielectric layers are formed without protective structures, then fabrication is simpler, but under-etching occurs relative to neighboring non-high-k features
Solution Approach 1:
The protective apron acts as an intermediary layer between the high-k dielectric and the etching process. It is deposited conformally over the high-k dielectric and then patterned to extend beyond the desired gate boundaries, providing a sacrificial shield that prevents the etch from undercutting the high-k dielectric relative to neighboring features, thereby ensuring feature uniformity
Solution Approach 2:
The protective apron and overhanging fin template extend the structure into the lateral dimension beyond the gate boundaries. The protective apron is formed with lateral overhang, and the fin template extends outward from the fin surface, creating a three-dimensional protective architecture that shields the high-k dielectric from etching in critical dimensions
3Manufacturing precision
If gate structure dimensions are not precisely controlled, then fabrication is easier, but gate length and positioning uniformity deteriorates
Solution Approach 1:
The overhanging fin template provides a self-aligned feedback mechanism for gate length control. The template is formed to extend beyond the desired gate boundaries by a predetermined amount, and this overhang serves as a visual and physical reference during subsequent etching steps, ensuring that the gate is etched to the correct dimensions with uniform positioning across all devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves improved dimension uniformity of high-k dielectric layers with neighboring non-high-k device features, preventing under-etching and ensuring precise control over the gate structure's length and positioning, enhancing the performance of VT FinFETs in logic and memory devices.
Implementation Method 1
a high-k dielectric layer is formed on the exposed surfaces of the bottom spacer layer, lower recess fillers, fin channel posts, upper recess fillers, and fin templates
Data Source
AI summary
A method of forming a vertical transport fin field effect transistor is provided. The method includes forming a doped layer on a substrate, and forming a multilayer fin on the doped layer, where the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the upper and lower trim layer portions. A portion of the lower trim layer portion is removed to form a lower trim layer post, and a portion of the upper trim layer portion is removed to form an upper trim layer post. An upper recess filler is formed adjacent to the upper trim layer post, and a lower recess filler is formed adjacent to the lower trim layer post. A portion of the fin channel portion is removed to form a fin channel post between the upper trim layer post and lower trim layer post.