High-k Dielectric Profile Shaping to Cut Parasitic Capacitance
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Solution Overview
Problem
In semiconductor device fabrication, non-planar transistor architectures face challenges in reducing parasitic capacitance, which affects device performance and integration density due to the conventional high-k dielectric structure profiles.
Innovation Solution
A method involving selective etching steps to form a wider and shallower high-k dielectric structure, reducing parasitic capacitance by creating a tilted and plateaued profile, thereby minimizing the coupling between gate structures and neighboring contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional high-k dielectric structure profile is used in non-planar transistor architectures, then the device structure is simpler to manufacture, but parasitic capacitance increases which degrades device performance and integration density
Solution Approach 1:
The high-k dielectric structure is segmented into multiple regions with different lateral extents: a first region extending over the channel structure and a second region extending over the contact structure. This segmentation allows different portions of the dielectric to serve different functions - the first region provides gate control while the second region is minimized to reduce parasitic capacitance. The selective removal of the second region further segments the structure to eliminate harmful capacitance effects.
Solution Approach 2:
The high-k dielectric structure exhibits local quality variations where different regions have different lateral extents and functional properties. The first region has a larger lateral extent to ensure proper gate control over the channel, while the second region has a minimized lateral extent over the contact structure to reduce parasitic capacitance. This local differentiation of dielectric properties optimizes both device performance and integration density.
2Reliability
If the high-k dielectric structure extends further laterally over the contact structure, then gate control is improved, but parasitic capacitance coupling between gate and contact increases
Solution Approach 1:
The dielectric structure is divided into functionally distinct segments: a first region providing gate control and a second region that would cause parasitic capacitance. By selectively removing the second region, the patent segments the harmful capacitive coupling path while preserving the beneficial gate control function in the first region.
Solution Approach 2:
The patent extracts and removes the second region of the high-k dielectric structure that extends over the contact structure. This extraction eliminates the source of parasitic capacitance coupling between the gate and contact while retaining the first region that provides necessary gate control, thus separating the harmful element from the beneficial element.
Data Source
AI summary
A semiconductor device includes a first channel structure extending along a first lateral direction and a second channel structure extending along the first lateral direction. The second channel structure is spaced apart from the first channel structure. The semiconductor device further includes a high-k dielectric structure extending along the first lateral direction and disposed between the first and second channel structures. The high-k dielectric structure has a bottom surface that comprises a bottommost portion and at least a first plateau portion elevated from the bottommost portion.