High-K Dielectric Etching via Remote Plasma Segmentation
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Solution Overview
Problem
Current methods for forming blocking dielectric layers in NAND type non-volatile memory devices using high-K materials face challenges in achieving high etching rates without damaging adjacent layers, which affects the capacitance and leakage current characteristics.
Innovation Solution
The method involves forming a high-K dielectric layer between other dielectric sub-layers and using isotropic and anisotropic etching techniques with remote plasma to selectively etch the high-K layer, ensuring high etching rates while minimizing damage to adjacent layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-K material is used to form blocking dielectric layer, then capacitance is improved and leakage current characteristics are improved, but etching rate is reduced and damage to adjacent layers occurs
Solution Approach 1:
The patent segments the etching process into two distinct stages: anisotropic etching to create the initial blocking dielectric layer structure, followed by isotropic etching to selectively remove the high-K material. This segmentation allows each etching mode to perform its optimal function without compromising the other.
Solution Approach 2:
The patent introduces an intermediary layer (such as a sacrificial layer or selectively etched layer) that facilitates the selective removal of high-K material. This intermediary enables the etching process to target specific regions without damaging adjacent sensitive layers, thereby maintaining high etching rates while protecting the overall structure.
2Reliability
If high-K material is used to form blocking dielectric layer, then capacitance is improved, but damage to adjacent layers occurs during etching
Solution Approach 1:
The patent introduces an intermediary layer (such as a sacrificial layer or selectively etched layer) that facilitates the selective removal of high-K material. This intermediary enables the etching process to target specific regions without damaging adjacent sensitive layers, thereby maintaining high etching rates while protecting the overall structure.
Solution Approach 2:
The patent applies different etching characteristics (anisotropic vs. isotropic) to different regions and stages of the process. The anisotropic etching is applied where directional precision is needed, while isotropic etching is applied where selective removal of high-K material is required, thereby locally optimizing the process to protect adjacent layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient removal of the high-K material with reduced risk of damaging adjacent layers, thereby improving the capacitance and leakage current characteristics of the blocking dielectric layers.
Implementation Method 1
The exposed portions of the second dielectric layer may be isotropically etched
Implementation Method 2
The exposed portions of the second silicon oxide layer may be isotropically etched using remote plasma
Implementation Method 3
The exposed portions of the second conductive layer may be anisotropically etched using the mask pattern to provide a control gate pattern
Data Source
AI summary
A method of forming a semiconductor device may include forming a first pattern on a substrate, and forming a first dielectric layer on the first pattern. The first pattern may be between portions of the first dielectric layer and the substrate. A second dielectric layer may be formed on the first dielectric layer, and the first dielectric layer may be between the first pattern and the second dielectric layer. A second pattern may be formed on the second dielectric layer. Portions of the second dielectric layer may be exposed by the second pattern, and the first and second dielectric layers may be between portions of the first and second patterns. The exposed portions of the second dielectric layer may be isotropically etched.