High-K Dielectric Interlayer for Leakage Reduction
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Solution Overview
Problem
Conventional semiconductor devices with thin SiO2 layers face issues such as stress-induced leakage current, exponential increase in leakage current with thickness reduction, and difficulty in maintaining thickness uniformity, which affect device reliability and scalability.
Innovation Solution
Incorporating high-K dielectric materials like Al2O3 and silicon nitride into the intergate dielectric layer to increase permittivity, allowing for a thinner electrical equivalent thickness while maintaining or increasing the physical thickness, thereby reducing leakage current and improving device scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
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If the SiO2 gate dielectric layer thickness is reduced to enable further device scaling, then device dimensions can be reduced, but leakage current increases exponentially and stress-induced leakage occurs
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate dielectric material from conventional SiO2 (K≈3.9) to high-K materials such as barium strontium titanate (BST) with K>100. This parameter change allows the dielectric layer to maintain lower electrical equivalent thickness (affecting device scaling) while having greater physical thickness (reducing leakage), thereby resolving the contradiction between device dimension reduction and leakage current control
Solution Approach 2:
The patent employs composite dielectric structures combining high-K materials (BST, barium titanate, strontium titanate) with silicon oxide layers. The high-K material provides the necessary permittivity for thin equivalent thickness, while the silicon oxide layers provide interface quality and leakage control, creating a composite structure that simultaneously achieves scaling and reliability
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If the SiO2 gate dielectric layer thickness is reduced to enable further device scaling, then device dimensions can be reduced, but manufacturing precision becomes difficult to maintain
Solution Approach 1:
By changing to high-K materials, the patent increases the physical thickness of the dielectric layer for a given electrical equivalent thickness. This increased physical thickness provides a larger manufacturing window, making it easier to maintain thickness uniformity and achieve precise control during fabrication processes, thereby resolving the manufacturing precision issue while still enabling device scaling
Solution Approach 2:
The patent introduces silicon oxide intermediary layers between the high-K dielectric material and the semiconductor substrate/gate electrode. These intermediary layers serve as buffer zones that facilitate controlled deposition and improve interface quality, making the overall structure more manufacturable with better thickness uniformity while maintaining the scaling benefits of the high-K material
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device reliability and scalability by reducing leakage current and maintaining data retention, while allowing for further reduction in device dimensions without compromising performance.
Implementation Method 1
Incorporating high-K dielectric materials like Al2O3 and silicon nitride into the intergate dielectric layer to increase permittivity, allowing for a thinner electrical equivalent thickness while maintaining or increasing the physical thickness, thereby reducing leakage current
Data Source
AI summary
In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO2; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO2.